diff --git a/README.md b/README.md index 718d2fae2f9b27a0823d8bad4ce95aa0a6c1b05a..c7644b95703e9cbf11518b1eed2f79e125b956a4 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ -# Machine Kit Router +# AutomataKit Router -This is a message passing / compute center for machines, robotics. +This is a message passing device and USB link for the [automatakit](https://gitlab.cba.mit.edu/jakeread/automatakit) architecture.  @@ -8,50 +8,25 @@ This is a message passing / compute center for machines, robotics.  -## Status -It works! If you have one, it should forward packets no problem. Let me know if you find weird errors... +## Development Notes -## Next Steps -Did a redesign for this using the ATSAMD51 and USB-Serial on-chip conversion so that networks can run at 1-3MBaud, not 0.1MBaud. That board is out to the house. +See [circuit chatter](/circuit) and [firmware chatter](/embedded). -# New Board +# Viable Commands -- is out to fab +### Test - +Keycode: **127** + - to test networking, this will reply with a payload packet containing ```127, 12, 24, 48``` and will toggle an LED on the board - +### Reset -# Board Design +Keycode: **128** + - issues a software microcontroller reset + - if the microcontroller is already hung up, this will not work -I use the ATSAMS70 micro, which is very fast but still simple enough. 300Mhz and the I/O we need. +# Reproducing This Work -That said, setting up the power schematic is messier than I would like. There's an internal regulator on the chip that is externally connected to a few 'vddcore' input pins (5), each of which needs a bypass cap. In addition, there are 5 vddio pins that supply voltage to the i/o lines. These also get bypass caps. This is 10 bypass caps. That is a lot to place right off the bat. In addition, there are some pesky vddpll lines that ask for filtered inputs from either the main line or the regulator, meaning I have now inductors and more bypass caps. Oh my. Here is the schematic checklist diagram: +All automatakit works are open source, and while we cannot sell you boards, if you have an interesting application, get in touch to ask about collaborating. - - -To do nice ADC things I want a well stabilized vrefp and vrefn, I will neglect doing this with this chip. - -Setting up the USB successfully is nontrivial, as it can be a properly high-speed differential line. I have bricked a few of these chips trying to implement the usb operation, so I'm going to skip most of this as well... Maybe breaking out the USBDM and USBDP lines just in case I get bored later, but I kind of doubt that. - -So, here it is. I didn't ask for this complexity. *grumbling* - - - -Less talk more routing ... one note - I am putting some ground plane between all of the RX and TX lines, which I hope to be driving around-and-above 3MHz. So, I want them to not be coupling into eachother. Leaving some ground plane between each trace is a bit like shielding a wire... Here you can see two of the ports taking 'the dive' to the ground plane, where they have lots of room, and then being routed with some space between. I should update other boards using similar rules as well - I'm re-doing my BLDC driver and have started a stepper board that I'll be bringing up at the same time, so I can do that. Nice. - - - -OK, here it is: - - - - - -# Notes - -PP7 is a miss, check others as well. - -Silk kind of messy. - -for all, make QFN64 footprint rock: the QFN for those tmc chips are awesome, follow suit \ No newline at end of file +To reproduce boards and load code, see the document ['Reproducing Automatakit Work'](https://gitlab.cba.mit.edu/jakeread/automatakit/reproducing) \ No newline at end of file diff --git a/circuit/README.md b/circuit/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3dcae746687c067b6d071064bccc1ce69e865037 --- /dev/null +++ b/circuit/README.md @@ -0,0 +1,7 @@ +# AutomataKit Router Circuit Design + + + + + +The circuit uses an ATxmega256A3U microcontroller and it's UART modules to chatter over 5 ports. It includes a CP2102n USB - UART bridge, acting as the 6th port, to receive serial messages from a computer. \ No newline at end of file diff --git a/circuit/atkrouter-v01/atkrouter-v01.brd b/circuit/atkrouter-v01/atkrouter-v01.brd new file mode 100644 index 0000000000000000000000000000000000000000..815fadd73376c6b0dca34a694023dd707c7a0cea --- /dev/null +++ b/circuit/atkrouter-v01/atkrouter-v01.brd @@ -0,0 +1,2224 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="9.0.0"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="mm" unit="mm" style="lines" multiple="1" display="yes" altdistance="5" altunitdist="mil" altunit="mil"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" 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gewählt, dass sie für +die meisten Anwendungen passen. Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="6mil"/> +<param name="mdWirePad" value="6mil"/> +<param name="mdWireVia" value="6mil"/> +<param name="mdPadPad" value="6mil"/> +<param name="mdPadVia" value="6mil"/> +<param name="mdViaVia" value="6mil"/> +<param name="mdSmdPad" value="6mil"/> +<param name="mdSmdVia" value="6mil"/> +<param name="mdSmdSmd" value="6mil"/> +<param name="mdViaViaSameLayer" value="6mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="8mil"/> +<param name="mdDrill" value="6mil"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="6mil"/> +<param name="msDrill" value="0.3mm"/> +<param name="msMicroVia" value="9.99mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0.25"/> +<param name="rvMicroViaInner" value="0.25"/> +<param name="rlMinPadTop" value="10mil"/> +<param name="rlMaxPadTop" value="20mil"/> +<param name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="8mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="8mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="4mil"/> +<param name="mlMaxStopFrame" value="4mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="25mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="8mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="checkStop" value="0"/> +<param name="checkValues" value="0"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="AutoGrid" value="1"/> +<param name="Efforts" value="0"/> +<param name="TopRouterVariant" value="1"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="a"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" 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name="N$7"> +<contactref element="R8" pad="2"/> +<contactref element="J6" pad="GRNN"/> +<wire x1="39.4" y1="35.51" x2="36.89" y2="33" width="0.1524" layer="1"/> +<wire x1="36.89" y1="33" x2="35.95" y2="33" width="0.1524" layer="1"/> +</signal> +<signal name="N$8"> +<contactref element="J6" pad="YLWN"/> +<contactref element="R9" pad="2"/> +<wire x1="39.4" y1="24.03" x2="36.87" y2="21.5" width="0.1524" layer="1"/> +<wire x1="36.87" y1="21.5" x2="35.95" y2="21.5" width="0.1524" layer="1"/> +</signal> +<signal name="N$9"> +<contactref element="R10" pad="2"/> +<contactref element="J7" pad="GRNN"/> +<wire x1="39.4" y1="17.01" x2="39.4" y2="16.4" width="0.1524" layer="1"/> +<wire x1="37.5" y1="14.5" x2="35.95" y2="14.5" width="0.1524" layer="1"/> +<wire x1="39.4" y1="16.4" x2="37.5" y2="14.5" width="0.1524" layer="1"/> +</signal> +<signal name="N$10"> +<contactref element="J7" pad="YLWN"/> +<contactref element="R11" pad="2"/> +<wire x1="39.4" y1="5.53" x2="36.87" y2="3" width="0.1524" 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x1="44.45" y1="69.07" x2="46.3" y2="67.22" width="0.1524" layer="16"/> +<wire x1="46.3" y1="60.6" x2="44.5" y2="58.8" width="0.1524" layer="16"/> +<wire x1="44.5" y1="58.8" x2="44.5" y2="50.62" width="0.1524" layer="16"/> +<wire x1="44.5" y1="50.62" x2="44.45" y2="50.57" width="0.1524" layer="16"/> +<wire x1="46.3" y1="67.22" x2="46.3" y2="60.6" width="0.1524" layer="16"/> +<wire x1="44.45" y1="50.57" x2="46" y2="49.02" width="0.1524" layer="1"/> +<wire x1="44.45" y1="40.65" x2="44.45" y2="32.07" width="0.1524" layer="1"/> +<wire x1="46" y1="49.02" x2="46" y2="42.2" width="0.1524" layer="1"/> +<wire x1="46" y1="42.2" x2="44.45" y2="40.65" width="0.1524" layer="1"/> +<wire x1="44.45" y1="32.07" x2="46.3" y2="30.22" width="0.1524" layer="16"/> +<wire x1="46.3" y1="23.7" x2="44.5" y2="21.9" width="0.1524" layer="16"/> +<wire x1="44.5" y1="21.9" x2="44.5" y2="13.62" width="0.1524" layer="16"/> +<wire x1="44.5" y1="13.62" x2="44.45" y2="13.57" width="0.1524" layer="16"/> +<wire x1="46.3" y1="30.22" x2="46.3" y2="23.7" width="0.1524" layer="16"/> +<contactref element="U1" pad="46"/> +<via x="24.7" y="61.8" extent="1-16" drill="0.3"/> +<wire x1="20" y1="59.85" x2="22.45" y2="59.85" width="0.1524" layer="1"/> +<wire x1="24.7" y1="83.1" x2="24.7" y2="61.8" width="0.1524" layer="16"/> +<wire x1="22.45" y1="59.85" x2="24.4" y2="61.8" width="0.1524" layer="1"/> +<wire x1="24.4" y1="61.8" x2="24.7" y2="61.8" width="0.1524" layer="1"/> +</signal> +</signals> +</board> +</drawing> +<compatibility> +<note version="6.3" minversion="6.2.2" severity="warning"> +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. +</note> +</compatibility> +</eagle> diff --git a/circuit/atkrouter-v01/atkrouter-v01.sch b/circuit/atkrouter-v01/atkrouter-v01.sch new file mode 100644 index 0000000000000000000000000000000000000000..146f16067d73c3f29a2ca0de62278d499eaa4fdc --- /dev/null +++ b/circuit/atkrouter-v01/atkrouter-v01.sch @@ -0,0 +1,3574 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="9.0.0"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> +<layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/> +<layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/> +<layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/> +<layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/> +<layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/> +<layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/> +<layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/> +<layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/> +<layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/> +<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/> +<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/> +<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/> +<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/> +<layer number="20" name="Dimension" color="24" fill="1" visible="no" active="no"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/> +<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/> +<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/> +<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/> +<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/> +<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/> +<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/> +<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/> +<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/> +<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/> +<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/> +<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/> +<layer number="33" name="tFinish" color="6" fill="3" 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fill="1" visible="yes" active="yes"/> +<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/> +<layer number="101" name="Patch_Top" color="12" fill="4" visible="no" active="yes"/> +<layer number="102" name="Vscore" color="7" fill="1" visible="no" active="yes"/> +<layer number="103" name="tMap" color="7" fill="1" visible="no" active="yes"/> +<layer number="104" name="Name" color="7" fill="1" visible="no" active="yes"/> +<layer number="105" name="tPlate" color="7" fill="1" visible="no" active="yes"/> +<layer number="106" name="bPlate" color="7" fill="1" visible="no" active="yes"/> +<layer number="107" name="Crop" color="7" fill="1" visible="no" active="yes"/> +<layer number="108" name="tplace-old" color="10" fill="1" visible="no" active="yes"/> +<layer number="109" name="ref-old" color="11" fill="1" visible="no" active="yes"/> +<layer number="110" name="fp0" color="7" fill="1" visible="no" active="yes"/> +<layer number="111" name="LPC17xx" color="7" fill="1" visible="no" active="yes"/> +<layer number="112" name="tSilk" color="7" fill="1" visible="no" active="yes"/> +<layer number="113" name="IDFDebug" color="7" fill="1" visible="no" active="yes"/> +<layer number="114" name="Badge_Outline" color="7" fill="1" visible="no" active="yes"/> +<layer number="115" name="ReferenceISLANDS" color="7" fill="1" visible="no" active="yes"/> +<layer number="116" name="Patch_BOT" color="9" fill="4" visible="no" active="yes"/> +<layer number="117" name="BACKMAAT1" color="7" fill="1" visible="yes" active="yes"/> +<layer number="118" name="Rect_Pads" color="7" fill="1" visible="no" active="yes"/> +<layer number="119" name="KAP_TEKEN" color="7" fill="1" visible="yes" active="yes"/> +<layer number="120" name="KAP_MAAT1" color="7" fill="1" visible="yes" active="yes"/> +<layer number="121" name="_tsilk" color="7" fill="1" visible="no" active="yes"/> +<layer number="122" name="_bsilk" color="7" fill="1" visible="no" active="yes"/> +<layer number="123" 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number="150" name="Notes" color="7" fill="1" visible="no" active="yes"/> +<layer number="151" name="HeatSink" color="7" fill="1" visible="no" active="yes"/> +<layer number="152" name="_bDocu" color="7" fill="1" visible="no" active="yes"/> +<layer number="153" name="FabDoc1" color="7" fill="1" visible="no" active="yes"/> +<layer number="154" name="FabDoc2" color="7" fill="1" visible="no" active="yes"/> +<layer number="155" name="FabDoc3" color="7" fill="1" visible="no" active="yes"/> +<layer number="199" name="Contour" color="7" fill="1" visible="no" active="yes"/> +<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="yes"/> +<layer number="201" name="201bmp" color="2" fill="10" visible="no" active="yes"/> +<layer number="202" name="202bmp" color="3" fill="10" visible="no" active="yes"/> +<layer number="203" name="203bmp" color="4" fill="10" visible="no" active="yes"/> +<layer number="204" name="204bmp" color="5" fill="10" visible="no" active="yes"/> +<layer number="205" name="205bmp" color="6" fill="10" visible="no" active="yes"/> +<layer number="206" name="206bmp" color="7" fill="10" visible="no" active="yes"/> +<layer number="207" name="207bmp" color="8" fill="10" visible="no" active="yes"/> +<layer number="208" name="208bmp" color="9" fill="10" visible="no" active="yes"/> +<layer number="209" name="209bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="210" name="210bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="211" name="211bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="212" name="212bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="213" name="213bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="214" name="214bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="215" name="215bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="216" name="216bmp" color="7" fill="1" visible="no" active="yes"/> +<layer number="217" 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x2="4.1" y2="-4.6" width="0.2032" layer="21"/> +<wire x1="4.6" y1="-4.6" x2="4.6" y2="-4.1" width="0.2032" layer="21"/> +<wire x1="-4.6" y1="-4.6" x2="-4.6" y2="-4.1" width="0.2032" layer="21"/> +<wire x1="-4.6" y1="-4.6" x2="-4.1" y2="-4.6" width="0.2032" layer="21"/> +<smd name="P$1" x="0" y="0" dx="7.6" dy="7.6" layer="1" cream="no"/> +<polygon width="0.127" layer="31"> +<vertex x="2.13" y="2.13"/> +<vertex x="2.13" y="3.27"/> +<vertex x="3.27" y="3.27"/> +<vertex x="3.27" y="2.13"/> +</polygon> +<polygon width="0.127" layer="31"> +<vertex x="-3.27" y="2.13"/> +<vertex x="-3.27" y="3.27"/> +<vertex x="-2.13" y="3.27"/> +<vertex x="-2.13" y="2.13"/> +</polygon> +<polygon width="0.127" layer="31"> +<vertex x="-3.27" y="-3.27"/> +<vertex x="-3.27" y="-2.13"/> +<vertex x="-2.13" y="-2.13"/> +<vertex x="-2.13" y="-3.27"/> +</polygon> +<polygon width="0.127" layer="31"> +<vertex x="2.13" y="-3.27"/> +<vertex x="2.13" y="-2.13"/> +<vertex x="3.27" y="-2.13"/> +<vertex x="3.27" y="-3.27"/> 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+<rectangle x1="-0.3" y1="-3.35" x2="0.3" y2="-2.55" layer="51" rot="R180"/> +<rectangle x1="2.24" y1="-3.35" x2="2.84" y2="-2.55" layer="51" rot="R180"/> +<smd name="1" x="-2.54" y="-2.85" dx="1.02" dy="1.9" layer="1"/> +<smd name="2" x="-2.54" y="2.85" dx="1.02" dy="1.9" layer="1"/> +<smd name="3" x="0" y="-2.85" dx="1.02" dy="1.9" layer="1"/> +<smd name="4" x="0" y="2.85" dx="1.02" dy="1.9" layer="1"/> +<smd name="5" x="2.54" y="-2.85" dx="1.02" dy="1.9" layer="1"/> +<smd name="6" x="2.54" y="2.85" dx="1.02" dy="1.9" layer="1"/> +<text x="-1.397" y="0.381" size="0.6096" layer="25" font="vector" ratio="20">>NAME</text> +<text x="-1.778" y="-1.016" size="0.6096" layer="27" font="vector" ratio="20">>VALUE</text> +<wire x1="-1.27" y1="-4.38" x2="1.27" y2="-4.38" width="0.2032" layer="21"/> +</package> +<package name="QFN-24_ALT2"> +<description><h3>24-pin QFN with Exposed Thermal pad</h3> +Parts that use this package: +<ul> +<li>A6282</li> +</ul> +Last modified: 8/20/10<br> +<br> +<b>***UNPROVEN***</b><BR></description> +<wire x1="-2" y1="-2" x2="-2" y2="2" width="0.127" layer="51"/> +<wire x1="-2" y1="2" x2="2" y2="2" width="0.127" layer="51"/> +<wire x1="2" y1="2" x2="2" y2="-2" width="0.127" layer="51"/> +<wire x1="2" y1="-2" x2="-2" y2="-2" width="0.127" layer="51"/> +<wire x1="-2" y1="1.6" x2="-1.6" y2="2" width="0.127" layer="21"/> +<wire x1="2" y1="2" x2="1.6" y2="2" width="0.127" layer="21"/> +<wire x1="2" y1="2" x2="2" y2="1.6" width="0.127" layer="21"/> +<wire x1="-2" y1="-2" x2="-1.6" y2="-2" width="0.127" layer="21"/> +<wire x1="-2" y1="-2" x2="-2" y2="-1.6" width="0.127" layer="21"/> +<wire x1="2" y1="-2" x2="2" y2="-1.6" width="0.127" layer="21"/> +<wire x1="2" y1="-2" x2="1.6" y2="-2" width="0.127" layer="21"/> +<smd name="21" x="0.25" y="2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="22" x="-0.25" y="2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="23" x="-0.75" y="2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="24" x="-1.25" y="2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="20" x="0.75" y="2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="19" x="1.25" y="2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="4" x="-2.05" y="-0.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="5" x="-2.05" y="-0.75" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="6" x="-2.05" y="-1.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="3" x="-2.05" y="0.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="2" x="-2.05" y="0.75" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="15" x="1.95" y="-0.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="14" x="1.95" y="-0.75" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="13" x="1.95" y="-1.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="16" x="1.95" y="0.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="17" x="1.95" y="0.75" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="10" x="0.25" y="-2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="9" x="-0.25" y="-2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="8" x="-0.75" y="-2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="7" x="-1.25" y="-2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="11" x="0.75" y="-2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="12" x="1.25" y="-2.05" dx="0.3" dy="0.9" layer="1"/> +<smd name="1" x="-2.05" y="1.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="18" x="1.95" y="1.25" dx="0.3" dy="0.9" layer="1" rot="R90"/> +<smd name="EP" x="0" y="0" dx="2.1" dy="2.1" layer="1" cream="no"/> +<rectangle x1="-0.9" y1="0.4" x2="-0.4" y2="0.9" layer="31"/> +<rectangle x1="0.4" y1="0.4" x2="0.9" y2="0.9" layer="31"/> +<rectangle x1="-0.9" y1="-0.9" x2="-0.4" y2="-0.4" layer="31"/> +<rectangle x1="0.4" y1="-0.9" x2="0.9" y2="-0.4" layer="31"/> +</package> +</packages> +<symbols> +<symbol name="ATXMEGA_A3U"> +<pin name="RESET/PDI_CLK" x="-25.4" y="66.04" length="middle"/> +<pin name="PDI_DATA" x="-25.4" y="60.96" length="middle"/> +<pin name="AVCC" x="-25.4" y="50.8" length="middle"/> +<pin name="VCC" x="-25.4" y="45.72" length="middle"/> +<pin name="GND" x="-25.4" y="38.1" length="middle"/> +<pin name="PR0/XTAL2" x="-25.4" y="7.62" length="middle"/> +<pin name="PR1/XTAL1" x="-25.4" y="-7.62" length="middle"/> +<pin name="PA0/AREF" x="25.4" y="66.04" length="middle" rot="R180"/> +<pin name="PA1" x="25.4" y="63.5" length="middle" rot="R180"/> +<pin name="PA2" x="25.4" y="60.96" length="middle" rot="R180"/> +<pin name="PA3" x="25.4" y="58.42" length="middle" rot="R180"/> +<pin name="PA4" x="25.4" y="55.88" length="middle" rot="R180"/> +<pin name="PA5" x="25.4" y="53.34" length="middle" rot="R180"/> +<pin name="PA6" x="25.4" y="50.8" length="middle" rot="R180"/> +<pin name="PA7" x="25.4" y="48.26" length="middle" rot="R180"/> +<pin name="PB0/AREF" x="25.4" y="43.18" length="middle" rot="R180"/> +<pin name="PB1" x="25.4" y="40.64" length="middle" rot="R180"/> +<pin name="PB2/DAC0" x="25.4" y="38.1" length="middle" rot="R180"/> +<pin name="PB3/DAC1" x="25.4" y="35.56" length="middle" rot="R180"/> +<pin name="PB4" x="25.4" y="33.02" length="middle" rot="R180"/> +<pin name="PB5" x="25.4" y="30.48" length="middle" rot="R180"/> +<pin name="PB6" x="25.4" y="27.94" length="middle" rot="R180"/> +<pin name="PB7" x="25.4" y="25.4" length="middle" rot="R180"/> +<pin name="PC0/SDA" x="25.4" y="20.32" length="middle" rot="R180"/> +<pin name="PC1/SCL/XCK0" x="25.4" y="17.78" length="middle" rot="R180"/> +<pin name="PC2/RXD0" x="25.4" y="15.24" length="middle" rot="R180"/> +<pin name="PC3/TXD0" x="25.4" y="12.7" length="middle" rot="R180"/> +<pin name="PC4/SS" x="25.4" y="10.16" length="middle" rot="R180"/> +<pin name="PC5/XCK1/MOSI" x="25.4" y="7.62" length="middle" rot="R180"/> +<pin name="PC6/RXD1/MISO" x="25.4" y="5.08" length="middle" rot="R180"/> +<pin name="PC7/TXD1/SCK" x="25.4" y="2.54" length="middle" rot="R180"/> +<pin name="PD0" x="25.4" y="-2.54" length="middle" rot="R180"/> +<pin name="PD1/XCK0" x="25.4" y="-5.08" length="middle" rot="R180"/> +<pin name="PD2/RXD0" x="25.4" y="-7.62" length="middle" rot="R180"/> +<pin name="PD3/TXD0" x="25.4" y="-10.16" length="middle" rot="R180"/> +<pin name="PD4/SS" x="25.4" y="-12.7" length="middle" rot="R180"/> +<pin name="PD5/XCK/MOSI" x="25.4" y="-15.24" length="middle" rot="R180"/> +<pin name="PD6/RXD1/MISO/D-" x="25.4" y="-17.78" length="middle" rot="R180"/> +<pin name="PD7/TXD1/SCK/D+" x="25.4" y="-20.32" length="middle" rot="R180"/> +<pin name="PE0/SDA" x="25.4" y="-25.4" length="middle" rot="R180"/> +<pin name="PE1/SCL/XCK0" x="25.4" y="-27.94" length="middle" rot="R180"/> +<pin name="PE2/RXD0" x="25.4" y="-30.48" length="middle" rot="R180"/> +<pin name="PE3/TXD0" x="25.4" y="-33.02" length="middle" rot="R180"/> +<pin name="PE4/SS" x="25.4" y="-35.56" length="middle" rot="R180"/> +<pin name="PE5/XCK1/MOSI" x="25.4" y="-38.1" length="middle" rot="R180"/> +<pin name="PE6/RXD1/MISO" x="25.4" y="-40.64" length="middle" rot="R180"/> +<pin name="PE7/TXD1/SCK" x="25.4" y="-43.18" length="middle" rot="R180"/> +<pin name="PF0" x="25.4" y="-48.26" length="middle" rot="R180"/> +<pin name="PF1/XCK0" x="25.4" y="-50.8" length="middle" rot="R180"/> +<pin name="PF2/RXD0" x="25.4" y="-53.34" length="middle" rot="R180"/> +<pin name="PF3/TXD0" x="25.4" y="-55.88" length="middle" rot="R180"/> +<pin name="PF4" x="25.4" y="-58.42" length="middle" rot="R180"/> +<pin name="PF5" x="25.4" y="-60.96" length="middle" rot="R180"/> +<pin name="PF6" x="25.4" y="-63.5" length="middle" rot="R180"/> +<pin name="PF7" x="25.4" y="-66.04" length="middle" rot="R180"/> +<wire x1="20.32" y1="68.58" x2="20.32" y2="-68.58" width="0.254" layer="94"/> +<wire x1="20.32" y1="-68.58" x2="-20.32" y2="-68.58" width="0.254" layer="94"/> +<wire x1="-20.32" y1="-68.58" x2="-20.32" y2="68.58" width="0.254" layer="94"/> +<wire x1="-20.32" y1="68.58" x2="20.32" y2="68.58" width="0.254" layer="94"/> +</symbol> +<symbol name="PDI"> +<description><h3>6 Pin Connection</h3> +3x2 pin layout</description> +<pin name="PDI_DATA" x="-15.24" y="2.54" length="middle"/> +<pin name="NC1" x="-15.24" y="0" length="middle"/> +<pin name="PDI_CLK" x="-15.24" y="-2.54" length="middle"/> +<pin name="GND" x="15.24" y="-2.54" length="middle" rot="R180"/> +<pin name="NC2" x="15.24" y="0" length="middle" rot="R180"/> +<pin name="VCC" x="15.24" y="2.54" length="middle" rot="R180"/> +<text x="-3.556" y="5.588" size="1.778" layer="95" font="vector">>NAME</text> +<text x="-3.302" y="-5.842" size="1.778" layer="96" font="vector" align="top-left">>VALUE</text> +<wire x1="-11.43" y1="5.08" x2="-11.43" y2="-5.08" width="0.4064" layer="94"/> +<wire x1="11.43" y1="-5.08" x2="-11.43" y2="-5.08" width="0.4064" layer="94"/> +<wire x1="11.43" y1="-5.08" x2="11.43" y2="5.08" width="0.4064" layer="94"/> +<wire x1="-11.43" y1="5.08" x2="11.43" y2="5.08" width="0.4064" layer="94"/> +</symbol> +<symbol name="CP2102N"> +<pin name="VIO" x="-20.32" y="22.86" length="middle"/> +<pin name="VREGIN" x="-20.32" y="15.24" length="middle"/> +<pin name="VDD" x="-20.32" y="7.62" length="middle"/> +<pin name="GND" x="-20.32" y="0" length="middle"/> +<pin name="VBUS" x="-20.32" y="-7.62" length="middle"/> +<pin name="DM" x="-20.32" y="-15.24" length="middle"/> +<pin name="DP" x="-20.32" y="-17.78" length="middle"/> +<pin name="RST_" x="-20.32" y="-25.4" length="middle"/> +<pin name="GPIO0/TXT" x="20.32" y="22.86" length="middle" rot="R180"/> +<pin name="GPIO1/RXT" x="20.32" y="20.32" length="middle" rot="R180"/> +<pin name="GPIO2" x="20.32" y="17.78" length="middle" rot="R180"/> +<pin name="GPIO3" x="20.32" y="15.24" length="middle" rot="R180"/> +<pin name="SUSPEND" x="20.32" y="7.62" length="middle" rot="R180"/> +<pin name="_SUSPEND" x="20.32" y="5.08" length="middle" rot="R180"/> +<pin name="RI/CLK" x="20.32" y="-2.54" length="middle" rot="R180"/> +<pin name="DCD" x="20.32" y="-5.08" length="middle" rot="R180"/> +<pin name="DTR" x="20.32" y="-7.62" length="middle" rot="R180"/> +<pin name="DSR" x="20.32" y="-10.16" length="middle" rot="R180"/> +<pin name="TXD" x="20.32" y="-15.24" length="middle" rot="R180"/> +<pin name="RXD" x="20.32" y="-17.78" length="middle" rot="R180"/> +<pin name="RTS" x="20.32" y="-22.86" length="middle" rot="R180"/> +<pin name="CTS" x="20.32" y="-25.4" length="middle" rot="R180"/> +<wire x1="-15.24" y1="-27.94" x2="-15.24" y2="25.4" width="0.254" layer="94"/> +<wire x1="-15.24" y1="25.4" x2="15.24" y2="25.4" width="0.254" layer="94"/> +<wire x1="15.24" y1="25.4" x2="15.24" y2="-27.94" width="0.254" layer="94"/> +<wire x1="15.24" y1="-27.94" x2="-15.24" y2="-27.94" width="0.254" layer="94"/> +<text x="-2.54" y="25.4" size="1.27" layer="95">>NAME</text> +<text x="-2.54" y="-30.48" size="1.27" layer="96">>VALUE</text> +</symbol> +</symbols> +<devicesets> +<deviceset name="ATXMEGA_A3U" prefix="U"> +<gates> +<gate name="G$1" symbol="ATXMEGA_A3U" x="0" y="0"/> +</gates> +<devices> +<device name="TQFP" package="TQFP64_14X14MM-013THIN"> +<connects> +<connect gate="G$1" pin="AVCC" pad="61"/> +<connect gate="G$1" pin="GND" pad="14 24 34 44 52 60"/> +<connect gate="G$1" pin="PA0/AREF" pad="62"/> +<connect gate="G$1" pin="PA1" pad="63"/> +<connect gate="G$1" pin="PA2" pad="64"/> +<connect gate="G$1" pin="PA3" pad="1"/> +<connect gate="G$1" pin="PA4" pad="2"/> +<connect gate="G$1" pin="PA5" pad="3"/> +<connect gate="G$1" pin="PA6" pad="4"/> +<connect gate="G$1" pin="PA7" pad="5"/> +<connect gate="G$1" pin="PB0/AREF" pad="6"/> +<connect gate="G$1" pin="PB1" pad="7"/> +<connect gate="G$1" pin="PB2/DAC0" pad="8"/> +<connect gate="G$1" pin="PB3/DAC1" pad="9"/> +<connect gate="G$1" pin="PB4" pad="10"/> +<connect gate="G$1" pin="PB5" pad="11"/> +<connect gate="G$1" pin="PB6" pad="12"/> +<connect gate="G$1" pin="PB7" pad="13"/> +<connect gate="G$1" pin="PC0/SDA" pad="16"/> +<connect gate="G$1" pin="PC1/SCL/XCK0" pad="17"/> +<connect gate="G$1" pin="PC2/RXD0" pad="18"/> +<connect gate="G$1" pin="PC3/TXD0" pad="19"/> +<connect gate="G$1" pin="PC4/SS" pad="20"/> +<connect gate="G$1" pin="PC5/XCK1/MOSI" pad="21"/> +<connect gate="G$1" pin="PC6/RXD1/MISO" pad="22"/> +<connect gate="G$1" pin="PC7/TXD1/SCK" pad="23"/> +<connect gate="G$1" pin="PD0" pad="26"/> +<connect gate="G$1" pin="PD1/XCK0" pad="27"/> +<connect gate="G$1" pin="PD2/RXD0" pad="28"/> +<connect gate="G$1" pin="PD3/TXD0" pad="29"/> +<connect gate="G$1" pin="PD4/SS" pad="30"/> +<connect gate="G$1" pin="PD5/XCK/MOSI" pad="31"/> +<connect gate="G$1" pin="PD6/RXD1/MISO/D-" pad="32"/> +<connect gate="G$1" pin="PD7/TXD1/SCK/D+" pad="33"/> +<connect gate="G$1" pin="PDI_DATA" pad="56"/> +<connect gate="G$1" pin="PE0/SDA" pad="36"/> +<connect gate="G$1" pin="PE1/SCL/XCK0" pad="37"/> +<connect gate="G$1" pin="PE2/RXD0" pad="38"/> +<connect gate="G$1" pin="PE3/TXD0" pad="39"/> +<connect gate="G$1" pin="PE4/SS" pad="40"/> +<connect gate="G$1" pin="PE5/XCK1/MOSI" pad="41"/> +<connect gate="G$1" pin="PE6/RXD1/MISO" pad="42"/> +<connect gate="G$1" pin="PE7/TXD1/SCK" pad="43"/> +<connect gate="G$1" pin="PF0" pad="46"/> +<connect gate="G$1" pin="PF1/XCK0" pad="47"/> +<connect gate="G$1" pin="PF2/RXD0" pad="48"/> +<connect gate="G$1" pin="PF3/TXD0" pad="49"/> +<connect gate="G$1" pin="PF4" pad="50"/> +<connect gate="G$1" pin="PF5" pad="51"/> +<connect gate="G$1" pin="PF6" pad="54"/> +<connect gate="G$1" pin="PF7" pad="55"/> +<connect gate="G$1" pin="PR0/XTAL2" pad="58"/> +<connect gate="G$1" pin="PR1/XTAL1" pad="59"/> +<connect gate="G$1" pin="RESET/PDI_CLK" pad="57"/> +<connect gate="G$1" pin="VCC" pad="15 25 35 45 53"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="QFN" package="QFN-64-9X9MM"> +<connects> +<connect gate="G$1" pin="AVCC" pad="61"/> +<connect gate="G$1" pin="GND" pad="14 24 34 44 52 60 P$1"/> +<connect gate="G$1" pin="PA0/AREF" pad="62"/> +<connect gate="G$1" pin="PA1" pad="63"/> +<connect gate="G$1" pin="PA2" pad="64"/> +<connect gate="G$1" pin="PA3" pad="1"/> +<connect gate="G$1" pin="PA4" pad="2"/> +<connect gate="G$1" pin="PA5" pad="3"/> +<connect gate="G$1" pin="PA6" pad="4"/> +<connect gate="G$1" pin="PA7" pad="5"/> +<connect gate="G$1" pin="PB0/AREF" pad="6"/> +<connect gate="G$1" pin="PB1" pad="7"/> +<connect gate="G$1" pin="PB2/DAC0" pad="8"/> +<connect gate="G$1" pin="PB3/DAC1" pad="9"/> +<connect gate="G$1" pin="PB4" pad="10"/> +<connect gate="G$1" pin="PB5" pad="11"/> +<connect gate="G$1" pin="PB6" pad="12"/> +<connect gate="G$1" pin="PB7" pad="13"/> +<connect gate="G$1" pin="PC0/SDA" pad="16"/> +<connect gate="G$1" pin="PC1/SCL/XCK0" pad="17"/> +<connect gate="G$1" pin="PC2/RXD0" pad="18"/> +<connect gate="G$1" pin="PC3/TXD0" pad="19"/> +<connect gate="G$1" pin="PC4/SS" pad="20"/> +<connect gate="G$1" pin="PC5/XCK1/MOSI" pad="21"/> +<connect gate="G$1" pin="PC6/RXD1/MISO" pad="22"/> +<connect gate="G$1" pin="PC7/TXD1/SCK" pad="23"/> +<connect gate="G$1" pin="PD0" pad="26"/> +<connect gate="G$1" pin="PD1/XCK0" pad="27"/> +<connect gate="G$1" pin="PD2/RXD0" pad="28"/> +<connect gate="G$1" pin="PD3/TXD0" pad="29"/> +<connect gate="G$1" pin="PD4/SS" pad="30"/> +<connect gate="G$1" pin="PD5/XCK/MOSI" pad="31"/> +<connect gate="G$1" pin="PD6/RXD1/MISO/D-" pad="32"/> +<connect gate="G$1" pin="PD7/TXD1/SCK/D+" pad="33"/> +<connect gate="G$1" pin="PDI_DATA" pad="56"/> +<connect gate="G$1" pin="PE0/SDA" pad="36"/> +<connect gate="G$1" pin="PE1/SCL/XCK0" pad="37"/> +<connect gate="G$1" pin="PE2/RXD0" pad="38"/> +<connect gate="G$1" pin="PE3/TXD0" pad="39"/> +<connect gate="G$1" pin="PE4/SS" pad="40"/> +<connect gate="G$1" pin="PE5/XCK1/MOSI" pad="41"/> +<connect gate="G$1" pin="PE6/RXD1/MISO" pad="42"/> +<connect gate="G$1" pin="PE7/TXD1/SCK" pad="43"/> +<connect gate="G$1" pin="PF0" pad="46"/> +<connect gate="G$1" pin="PF1/XCK0" pad="47"/> +<connect gate="G$1" pin="PF2/RXD0" pad="48"/> +<connect gate="G$1" pin="PF3/TXD0" pad="49"/> +<connect gate="G$1" pin="PF4" pad="50"/> +<connect gate="G$1" pin="PF5" pad="51"/> +<connect gate="G$1" pin="PF6" pad="54"/> +<connect gate="G$1" pin="PF7" pad="55"/> +<connect gate="G$1" pin="PR0/XTAL2" pad="58"/> +<connect gate="G$1" pin="PR1/XTAL1" pad="59"/> +<connect gate="G$1" pin="RESET/PDI_CLK" pad="57"/> +<connect gate="G$1" pin="VCC" pad="15 25 35 45 53"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="PDI" prefix="J" uservalue="yes"> +<description><h3>Multi connection point. Often used as Generic Header-pin footprint for 0.1 inch spaced/style header connections</h3> + +<p></p> + +<p></p> +<b>You can populate with any combo of single row headers, but if you'd like an exact match, check these:</b> +<ul> +<li><a href="https://www.sparkfun.com/products/12807"> Header - 2x3 (Male, 0.1")</a> (PRT-12807)</li> +<li><a href="https://www.sparkfun.com/products/13010"> Header - 2x3 (Female, 0.1")</a> (PRT-13010)</li> +<li><a href="https://www.sparkfun.com/products/10877"> 2x3 Pin Shrouded Header</a> (PRT-10877)</li> +</ul> + +<p></p> +<b>On any of the 0.1 inch spaced packages, you can populate with these:</b> +<ul> +<li><a href="https://www.sparkfun.com/products/116"> Break Away Headers - Straight</a> (PRT-00116)</li> +<li><a href="https://www.sparkfun.com/products/553"> Break Away Male Headers - Right Angle</a> (PRT-00553)</li> +<li><a href="https://www.sparkfun.com/products/115"> Female Headers</a> (PRT-00115)</li> +<li><a href="https://www.sparkfun.com/products/117"> Break Away Headers - Machine Pin</a> (PRT-00117)</li> +<li><a href="https://www.sparkfun.com/products/743"> Break Away Female Headers - Swiss Machine Pin</a> (PRT-00743)</li> +</ul> + +<p></p> +<b>Special note: the shrouded connector mates well with our 3x2 ribbon cables:</b> +<ul> +<li><a href="https://www.sparkfun.com/products/10651"> Ribbon Crimp Connector - 6-pin (2x3, Female)</a> (PRT-10651)</li> +<li><a href="https://www.sparkfun.com/products/10646"> Ribbon Cable - 6 wire (15ft)</a> (PRT-10646)</li> +</ul></description> +<gates> +<gate name="G$1" symbol="PDI" x="0" y="0"/> +</gates> +<devices> +<device name="FEMALE_SMD" package="PDI_2X3_SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="6"/> +<connect gate="G$1" pin="NC1" pad="3"/> +<connect gate="G$1" pin="NC2" pad="4"/> +<connect gate="G$1" pin="PDI_CLK" pad="5"/> +<connect gate="G$1" pin="PDI_DATA" pad="1"/> +<connect gate="G$1" pin="VCC" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11290"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="CP2102N" prefix="U"> +<gates> +<gate name="G$1" symbol="CP2102N" x="0" y="0"/> +</gates> +<devices> +<device name="" package="QFN-24_ALT2"> +<connects> +<connect gate="G$1" pin="CTS" pad="18"/> +<connect gate="G$1" pin="DCD" pad="24"/> +<connect gate="G$1" pin="DM" pad="4"/> +<connect gate="G$1" pin="DP" pad="3"/> +<connect gate="G$1" pin="DSR" pad="22"/> +<connect gate="G$1" pin="DTR" pad="23"/> +<connect gate="G$1" pin="GND" pad="2 EP"/> +<connect gate="G$1" pin="GPIO0/TXT" pad="14"/> +<connect gate="G$1" pin="GPIO1/RXT" pad="13"/> +<connect gate="G$1" pin="GPIO2" pad="12"/> +<connect gate="G$1" pin="GPIO3" pad="11"/> +<connect gate="G$1" pin="RI/CLK" pad="1"/> +<connect gate="G$1" pin="RST_" pad="9"/> +<connect gate="G$1" pin="RTS" pad="19"/> +<connect gate="G$1" pin="RXD" pad="20"/> +<connect gate="G$1" pin="SUSPEND" pad="17"/> +<connect gate="G$1" pin="TXD" pad="21"/> +<connect gate="G$1" pin="VBUS" pad="8"/> +<connect gate="G$1" pin="VDD" pad="6"/> +<connect gate="G$1" pin="VIO" pad="5"/> +<connect gate="G$1" pin="VREGIN" pad="7"/> +<connect gate="G$1" pin="_SUSPEND" pad="15"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="lights"> +<packages> +<package name="LED1206"> +<description>LED 1206 pads (standard pattern)</description> +<wire x1="0.9525" y1="-0.8128" x2="-0.9652" y2="-0.8128" width="0.1524" layer="51"/> +<wire x1="0.9525" y1="0.8128" x2="-0.9652" y2="0.8128" width="0.1524" layer="51"/> +<wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/> +<wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/> +<wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/> +<wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" 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layer="94"/> +<text x="3.556" y="-2.032" size="1.778" layer="95" rot="R90">>NAME</text> +<text x="5.715" y="-2.032" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="C" x="0" y="-2.54" visible="off" length="short" direction="pas" rot="R90"/> +<pin name="A" x="0" y="5.08" visible="off" length="short" direction="pas" rot="R270"/> +<polygon width="0.1524" layer="94"> +<vertex x="-3.429" y="0.381"/> +<vertex x="-3.048" y="1.27"/> +<vertex x="-2.54" y="0.762"/> +</polygon> +<polygon width="0.1524" layer="94"> +<vertex x="-3.302" y="-0.762"/> +<vertex x="-2.921" y="0.127"/> +<vertex x="-2.413" y="-0.381"/> +</polygon> +</symbol> +</symbols> +<devicesets> +<deviceset name="LED" prefix="D"> +<description>LED</description> +<gates> +<gate name="G$1" symbol="LED" x="0" y="0"/> +</gates> +<devices> +<device name="" package="LED1206"> +<connects> +<connect gate="G$1" pin="A" pad="1"/> +<connect gate="G$1" pin="C" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="FAB1206" package="LED1206FAB"> +<connects> +<connect gate="G$1" pin="A" pad="1"/> +<connect gate="G$1" pin="C" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="5MM" package="5MM"> +<connects> +<connect gate="G$1" pin="A" pad="IN"/> +<connect gate="G$1" pin="C" pad="OUT"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0805" package="LED0805"> +<connects> +<connect gate="G$1" pin="A" pad="1"/> +<connect gate="G$1" pin="C" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="connector"> +<packages> +<package name="JRTOMBSTONE"> +<wire x1="-1.1" y1="-1" x2="-1.1" y2="0.7" width="0.127" layer="21"/> +<wire x1="-1.1" y1="0.7" x2="1" y2="0.7" width="0.127" layer="21" curve="-180"/> +<wire x1="1" y1="0.7" x2="1" y2="-1" width="0.127" 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y2="-1.016" width="0.1524" layer="94"/> +<wire x1="-1.524" y1="-1.016" x2="-0.889" y2="1.016" width="0.1524" layer="94"/> +<wire x1="-0.889" y1="1.016" x2="-0.254" y2="-1.016" width="0.1524" layer="94"/> +<wire x1="-0.254" y1="-1.016" x2="0.381" y2="1.016" width="0.1524" layer="94"/> +<wire x1="0.381" y1="1.016" x2="1.016" y2="-1.016" width="0.1524" layer="94"/> +<wire x1="1.016" y1="-1.016" x2="1.651" y2="1.016" width="0.1524" layer="94"/> +<wire x1="1.651" y1="1.016" x2="2.286" y2="-1.016" width="0.1524" layer="94"/> +<wire x1="2.286" y1="-1.016" x2="2.54" y2="0" width="0.1524" layer="94"/> +<text x="-3.81" y="1.4986" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-3.302" size="1.778" layer="96">>VALUE</text> +<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> +<pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> +<text x="-3.81" y="-6.858" size="1.27" layer="97">>PRECISION</text> +<text x="-3.81" y="-5.08" size="1.27" layer="97">>PACKAGE</text> +</symbol> +<symbol name="CAP"> +<wire x1="0" y1="2.54" x2="0" y2="2.032" width="0.1524" layer="94"/> +<wire x1="0" y1="0" x2="0" y2="0.508" width="0.1524" layer="94"/> +<text x="1.524" y="2.921" size="1.778" layer="95">>NAME</text> +<text x="1.524" y="-2.159" size="1.778" layer="96">>VALUE</text> +<rectangle x1="-2.032" y1="0.508" x2="2.032" y2="1.016" layer="94"/> +<rectangle x1="-2.032" y1="1.524" x2="2.032" y2="2.032" layer="94"/> +<pin name="1" x="0" y="5.08" visible="off" length="short" direction="pas" swaplevel="1" rot="R270"/> +<pin name="2" x="0" y="-2.54" visible="off" length="short" direction="pas" swaplevel="1" rot="R90"/> +<text x="1.524" y="-4.064" size="1.27" layer="97">>PACKAGE</text> +<text x="1.524" y="-5.842" size="1.27" layer="97">>VOLTAGE</text> +<text x="1.524" y="-7.62" size="1.27" layer="97">>TYPE</text> +</symbol> +<symbol name="CERAMIC_RESONATOR"> +<wire x1="-5.08" y1="2.54" x2="5.08" y2="2.54" width="0.254" layer="94"/> +<wire x1="5.08" y1="2.54" x2="5.08" y2="0" width="0.254" layer="94"/> +<wire x1="5.08" y1="0" x2="5.08" y2="-5.08" width="0.254" layer="94"/> +<wire x1="5.08" y1="-5.08" x2="0" y2="-5.08" width="0.254" layer="94"/> +<wire x1="0" y1="-5.08" x2="-5.08" y2="-5.08" width="0.254" layer="94"/> +<wire x1="-5.08" y1="-5.08" x2="-5.08" y2="0" width="0.254" layer="94"/> +<wire x1="-5.08" y1="0" x2="-5.08" y2="2.54" width="0.254" layer="94"/> +<wire x1="-5.08" y1="0" x2="-3.81" y2="0" width="0.1524" layer="94"/> +<wire x1="-3.81" y1="0" x2="-1.27" y2="0" width="0.1524" layer="94"/> +<wire x1="-1.27" y1="0" x2="-1.27" y2="1.27" width="0.1524" layer="94"/> +<wire x1="-1.27" y1="0" x2="-1.27" y2="-1.27" width="0.1524" layer="94"/> +<wire x1="-0.508" y1="1.27" x2="-0.508" y2="-1.27" width="0.1524" layer="94"/> +<wire x1="-0.508" y1="-1.27" x2="0.508" y2="-1.27" width="0.1524" layer="94"/> +<wire x1="0.508" y1="-1.27" x2="0.508" y2="1.27" width="0.1524" layer="94"/> +<wire x1="0.508" y1="1.27" x2="-0.508" y2="1.27" width="0.1524" layer="94"/> +<wire x1="1.27" y1="1.27" x2="1.27" y2="0" width="0.1524" layer="94"/> +<wire x1="1.27" y1="0" x2="1.27" y2="-1.27" width="0.1524" layer="94"/> +<wire x1="1.27" y1="0" x2="3.81" y2="0" width="0.1524" layer="94"/> +<wire x1="3.81" y1="0" x2="5.08" y2="0" width="0.1524" layer="94"/> +<wire x1="0" y1="-5.08" x2="0" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="0" y1="-3.302" x2="-1.778" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="0" y1="-3.302" x2="1.778" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="1.778" y1="-2.286" x2="1.778" y2="-4.318" width="0.1524" layer="94"/> +<wire x1="2.54" y1="-2.286" x2="2.54" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="2.54" y1="-3.302" x2="2.54" y2="-4.318" width="0.1524" layer="94"/> +<wire x1="2.54" y1="-3.302" x2="3.81" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="3.81" y1="-3.302" x2="3.81" y2="0" width="0.1524" layer="94"/> +<wire x1="-1.778" y1="-2.286" x2="-1.778" y2="-4.318" width="0.1524" layer="94"/> +<wire x1="-2.54" y1="-2.286" x2="-2.54" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="-2.54" y1="-3.302" x2="-2.54" y2="-4.318" width="0.1524" layer="94"/> +<wire x1="-2.54" y1="-3.302" x2="-3.81" y2="-3.302" width="0.1524" layer="94"/> +<wire x1="-3.81" y1="-3.302" x2="-3.81" y2="0" width="0.1524" layer="94"/> +<circle x="-3.81" y="0" radius="0.254" width="0" layer="94"/> +<circle x="3.81" y="0" radius="0.254" width="0" layer="94"/> +<circle x="0" y="-3.302" radius="0.254" width="0" layer="94"/> +<text x="-5.08" y="3.81" size="1.778" layer="95">>NAME</text> +<text x="2.54" y="-7.62" size="1.778" layer="96">>VALUE</text> +<pin name="1" x="-7.62" y="0" visible="pad" length="short" direction="pas"/> +<pin name="2" x="0" y="-7.62" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="3" x="7.62" y="0" visible="pad" length="short" direction="pas" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="2-8X4-5_SWITCH" prefix="S"> +<gates> +<gate name="G$1" symbol="TS2" x="0" y="0"/> +</gates> +<devices> +<device name="" package="TACT-SWITCH-KMR6"> +<connects> +<connect gate="G$1" pin="P" pad="P$1"/> +<connect gate="G$1" pin="P1" pad="P$2"/> +<connect gate="G$1" pin="S" pad="P$3"/> +<connect gate="G$1" pin="S1" pad="P$4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<description><b>Resistor</b> +Basic schematic elements and footprints for 0603, 1206, and PTH resistors.</description> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="1206" constant="no"/> +<attribute name="PRECISION" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="2010" package="R2010"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="2010"/> +<attribute name="PRECISION" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="0805-RES" package="0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="0805"/> +<attribute name="PRECISION" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="0603-RES" package="0603-RES"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="0603"/> +<attribute name="PRECISION" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="0402-RES" package="0402-RES"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="0402"/> +<attribute name="PRECISION" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="2512" package="R2512"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="2512"/> +<attribute name="PRECISION" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TO220ACS" package="TO220ACS"> +<connects> +<connect gate="G$1" pin="1" pad="A"/> +<connect gate="G$1" pin="2" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="CAP" prefix="C" uservalue="yes"> +<description><b>Capacitor</b> +Standard 0603 ceramic capacitor, and 0.1" leaded capacitor.</description> +<gates> +<gate name="G$1" symbol="CAP" x="0" y="0"/> +</gates> +<devices> +<device name="0805" package="0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="0805"/> +<attribute name="TYPE" value="" constant="no"/> +<attribute name="VOLTAGE" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="0603-CAP" package="0603-CAP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="0603"/> +<attribute name="TYPE" value="" constant="no"/> +<attribute name="VOLTAGE" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="0402-CAP" package="0402-CAP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="0402"/> +<attribute name="TYPE" value="" constant="no"/> +<attribute name="VOLTAGE" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="1210" package="1210"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="1210" constant="no"/> +<attribute name="TYPE" value="" constant="no"/> +<attribute name="VOLTAGE" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PACKAGE" value="1206" constant="no"/> +<attribute name="TYPE" value="" constant="no"/> +<attribute name="VOLTAGE" value="" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESONATOR" prefix="Y"> +<gates> +<gate name="G$1" symbol="CERAMIC_RESONATOR" x="0" y="0"/> +</gates> +<devices> +<device name="" package="RES_EFOBM"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PQRC" package="RES_PRQC"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="supply1" urn="urn:adsk.eagle:library:371"> +<description><b>Supply Symbols</b><p> + GND, VCC, 0V, +5V, -5V, etc.<p> + Please keep in mind, that these devices are necessary for the + automatic wiring of the supply signals.<p> + The pin name defined in the symbol is identical to the net which is to be wired automatically.<p> + In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p> + <author>Created by librarian@cadsoft.de</author></description> +<packages> +</packages> +<symbols> +<symbol name="GND" urn="urn:adsk.eagle:symbol:26925/1" library_version="1"> +<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="-2.54" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +<symbol name="+3V3" urn="urn:adsk.eagle:symbol:26950/1" library_version="1"> +<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/> +<text x="-2.54" y="-5.08" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="GND" urn="urn:adsk.eagle:component:26954/1" prefix="GND" library_version="1"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="+3V3" urn="urn:adsk.eagle:component:26981/1" prefix="+3V3" library_version="1"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="G$1" symbol="+3V3" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="U1" library="microcontrollers" deviceset="ATXMEGA_A3U" device="QFN"/> +<part name="D1" library="lights" deviceset="LED" device="0805" value="LED0805RX"/> +<part name="MP1" library="connector" deviceset="JRTOMBSTONE" device=""/> +<part name="U2" library="power" deviceset="BUCK-TS30011-12-13" device="QFN"/> +<part name="J1" library="power" deviceset="PWRPAD" device="M2.5" value="PWRPADM2.5"/> +<part name="S1" library="passives" deviceset="2-8X4-5_SWITCH" device=""/> +<part name="R1" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="C1" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="C2" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="L1" library="power" deviceset="INDUCTOR" device="" value="4.7uH"/> +<part name="X1" library="connector" deviceset="MICRO-USB" device="_ORIG"/> +<part name="Y1" library="passives" deviceset="RESONATOR" device="PQRC"/> +<part name="J2" library="microcontrollers" deviceset="PDI" device="FEMALE_SMD"/> +<part name="J3" library="connector" deviceset="ATK-PHY" device=""/> +<part name="R2" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="R3" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="GND1" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V1" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="GND2" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V2" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="J4" library="connector" deviceset="ATK-PHY" device=""/> +<part name="R4" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="R5" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="GND3" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V3" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="J5" library="connector" deviceset="ATK-PHY" device=""/> +<part name="R6" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="R7" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="GND4" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V4" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="J6" library="connector" deviceset="ATK-PHY" device=""/> +<part name="R8" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="R9" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="GND5" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V5" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="J7" library="connector" deviceset="ATK-PHY" device=""/> +<part name="R10" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="R11" library="passives" deviceset="RESISTOR" device="0805-RES" value="150R"/> +<part name="GND6" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V6" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="C3" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="C4" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="C5" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="C6" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="GND8" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V8" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="U3" library="connector" deviceset="RASPBERRYPI-3BPLUS" device=""/> +<part name="J9" library="power" deviceset="PWRPAD" device="M2.5" value="PWRPADM2.5"/> +<part name="GND9" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V9" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="GND10" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="J10" library="connector" deviceset="POGO" device=""/> +<part name="J11" library="connector" deviceset="POGO" device=""/> +<part name="J12" library="connector" deviceset="POGO" device=""/> +<part name="J13" library="connector" deviceset="POGO" device=""/> +<part name="GND11" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="GND12" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="C7" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="C8" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="GND13" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="C9" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="C10" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="C11" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="GND14" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V10" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="GND15" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="+3V11" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="C12" library="passives" deviceset="CAP" device="0603-CAP" value="0.1uF"/> +<part name="C13" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="U$1" library="connector" deviceset="SOLDER_JUMPER" device=""/> +<part name="D2" library="lights" deviceset="LED" device="0805" value="LED0805TX"/> +<part name="R14" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="R15" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="+3V12" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="D3" library="lights" deviceset="LED" device="0805" value="LED0805RX"/> +<part name="+3V13" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="R16" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="D4" library="lights" deviceset="LED" device="0805" value="LED0805RX"/> +<part name="+3V14" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="R17" library="passives" deviceset="RESISTOR" device="0805-RES" value="470R"/> +<part name="D5" library="lights" deviceset="LED" device="0805" value="LED0805RX"/> +<part name="+3V15" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="GND17" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/> +<part name="C15" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="C16" library="passives" deviceset="CAP" device="1206" value="10uF"/> +<part name="J14" library="power" deviceset="PWRPAD" device="M2.5" value="PWRPADM2.5"/> +<part name="J8" library="power" deviceset="PWRPAD" device="M2.5" value="PWRPADM2.5"/> +<part name="U$3" library="connector" deviceset="FIDUCIAL" device=""/> +<part name="U$4" library="connector" deviceset="FIDUCIAL" device=""/> +<part name="U4" library="microcontrollers" deviceset="CP2102N" device=""/> +<part name="+3V7" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/> +<part name="R12" library="passives" deviceset="RESISTOR" device="0805-RES" value="10k"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="U1" gate="G$1" x="43.18" y="91.44"/> +<instance part="D1" gate="G$1" x="116.84" y="269.24" rot="R270"/> +<instance part="MP1" gate="G$1" x="27.94" y="2.54"/> +<instance part="U2" gate="G$1" x="53.34" y="180.34"/> +<instance part="J1" gate="G$1" x="25.4" y="-15.24" rot="R180"/> +<instance part="S1" gate="G$1" x="-27.94" y="170.18" rot="R270"/> +<instance part="R1" gate="G$1" x="119.38" y="200.66"/> +<instance part="C1" gate="G$1" x="5.08" y="132.08"/> +<instance part="C2" gate="G$1" x="106.68" y="177.8"/> +<instance part="L1" gate="G$1" x="91.44" y="182.88" rot="R270"/> +<instance part="X1" gate="G$1" x="-68.58" y="236.22" rot="R270"/> +<instance part="Y1" gate="G$1" x="5.08" y="91.44" rot="R270"/> +<instance part="J2" gate="G$1" x="-38.1" y="154.94" rot="R180"/> +<instance part="J3" gate="G$1" x="213.36" y="142.24"/> +<instance part="R2" gate="G$1" x="193.04" y="132.08"/> +<instance part="R3" gate="G$1" x="180.34" y="127"/> +<instance part="GND1" gate="1" x="137.16" y="20.32"/> +<instance part="+3V1" gate="G$1" x="132.08" y="25.4"/> +<instance part="GND2" gate="1" x="175.26" y="142.24" rot="R270"/> +<instance part="+3V2" gate="G$1" x="180.34" y="137.16" rot="R90"/> +<instance part="J4" gate="G$1" x="213.36" y="96.52"/> +<instance part="R4" gate="G$1" x="193.04" y="86.36"/> +<instance part="R5" gate="G$1" x="180.34" y="81.28"/> +<instance part="GND3" gate="1" x="175.26" y="96.52" rot="R270"/> +<instance part="+3V3" gate="G$1" x="180.34" y="91.44" rot="R90"/> +<instance part="J5" gate="G$1" x="213.36" y="50.8"/> +<instance part="R6" gate="G$1" x="193.04" y="40.64"/> +<instance part="R7" gate="G$1" x="180.34" y="35.56"/> +<instance part="GND4" gate="1" x="175.26" y="50.8" rot="R270"/> +<instance part="+3V4" gate="G$1" x="180.34" y="45.72" rot="R90"/> +<instance part="J6" gate="G$1" x="213.36" y="5.08"/> +<instance part="R8" gate="G$1" x="193.04" y="-5.08"/> +<instance part="R9" gate="G$1" x="180.34" y="-10.16"/> +<instance part="GND5" gate="1" x="175.26" y="5.08" rot="R270"/> +<instance part="+3V5" gate="G$1" x="180.34" y="0" rot="R90"/> +<instance part="J7" gate="G$1" x="213.36" y="-40.64"/> +<instance part="R10" gate="G$1" x="193.04" y="-50.8"/> +<instance part="R11" gate="G$1" x="180.34" y="-55.88"/> +<instance part="GND6" gate="1" x="175.26" y="-40.64" rot="R270"/> +<instance part="+3V6" gate="G$1" x="180.34" y="-45.72" rot="R90"/> +<instance part="C3" gate="G$1" x="-7.62" y="132.08"/> +<instance part="C4" gate="G$1" x="-20.32" y="132.08"/> +<instance part="C5" gate="G$1" x="-33.02" y="132.08"/> +<instance part="C6" gate="G$1" x="-45.72" y="132.08"/> +<instance part="GND8" gate="1" x="-60.96" y="129.54" rot="R270"/> +<instance part="+3V8" gate="G$1" x="-60.96" y="137.16" rot="R90"/> +<instance part="U3" gate="G$1" x="25.4" y="-10.16"/> +<instance part="J9" gate="G$1" x="25.4" y="-25.4" rot="R180"/> +<instance part="GND9" gate="1" x="-7.62" y="91.44" rot="R270"/> +<instance part="+3V9" gate="G$1" x="-60.96" y="152.4" rot="R90"/> +<instance part="GND10" gate="1" x="-60.96" y="157.48" rot="R270"/> +<instance part="J10" gate="G$1" x="-22.86" y="241.3" rot="R90"/> +<instance part="J11" gate="G$1" x="-48.26" y="226.06" rot="R270"/> +<instance part="J12" gate="G$1" x="-35.56" y="228.6" rot="R270"/> +<instance part="J13" gate="G$1" x="-48.26" y="243.84" rot="R90"/> +<instance part="GND11" gate="1" x="-33.02" y="238.76" rot="R90"/> +<instance part="GND12" gate="1" x="17.78" y="172.72" rot="R270"/> +<instance part="C7" gate="G$1" x="73.66" y="185.42"/> +<instance part="C8" gate="G$1" x="33.02" y="198.12"/> +<instance part="GND13" gate="1" x="33.02" y="208.28" rot="R180"/> +<instance part="C9" gate="G$1" x="116.84" y="177.8"/> +<instance part="C10" gate="G$1" x="127" y="177.8"/> +<instance part="C11" gate="G$1" x="137.16" y="177.8"/> +<instance part="GND14" gate="1" x="172.72" y="175.26" rot="R90"/> +<instance part="+3V10" gate="G$1" x="172.72" y="182.88" rot="R270"/> +<instance part="GND15" gate="1" x="-7.62" y="248.92" rot="R270"/> +<instance part="+3V11" gate="G$1" x="-7.62" y="264.16" rot="R90"/> +<instance part="C12" gate="G$1" x="10.16" y="254"/> +<instance part="C13" gate="G$1" x="0" y="254"/> +<instance part="U$1" gate="G$1" x="30.48" y="182.88"/> +<instance part="D2" gate="G$1" x="129.54" y="271.78" rot="R270"/> +<instance part="R14" gate="G$1" x="91.44" y="269.24"/> +<instance part="R15" gate="G$1" x="104.14" y="271.78"/> +<instance part="+3V12" gate="G$1" x="149.86" y="271.78" rot="R270"/> +<instance part="D3" gate="G$1" x="132.08" y="200.66" rot="R270"/> +<instance part="+3V13" gate="G$1" x="149.86" y="200.66" rot="R270"/> +<instance part="R16" gate="G$1" x="119.38" y="213.36"/> +<instance part="D4" gate="G$1" x="132.08" y="213.36" rot="R270"/> +<instance part="+3V14" gate="G$1" x="149.86" y="213.36" rot="R270"/> +<instance part="R17" gate="G$1" x="119.38" y="226.06"/> +<instance part="D5" gate="G$1" x="132.08" y="226.06" rot="R270"/> +<instance part="+3V15" gate="G$1" x="149.86" y="226.06" rot="R270"/> +<instance part="GND17" gate="1" x="96.52" y="200.66" rot="R270"/> +<instance part="C15" gate="G$1" x="149.86" y="177.8"/> +<instance part="C16" gate="G$1" x="162.56" y="177.8"/> +<instance part="J14" gate="G$1" x="48.26" y="-25.4" rot="R180"/> +<instance part="J8" gate="G$1" x="48.26" y="-15.24" rot="R180"/> +<instance part="U$3" gate="G$1" x="20.32" y="-38.1"/> +<instance part="U$4" gate="G$1" x="66.04" y="-5.08"/> +<instance part="U4" gate="G$1" x="48.26" y="248.92"/> +<instance part="+3V7" gate="G$1" x="-7.62" y="223.52" rot="R90"/> +<instance part="R12" gate="G$1" x="12.7" y="223.52"/> +</instances> +<busses> +</busses> +<nets> +<net name="ATK0-RXLED" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="187.96" y1="132.08" x2="160.02" y2="132.08" width="0.1524" layer="91"/> +<label x="160.02" y="132.08" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE4/SS"/> +<wire x1="68.58" y1="55.88" x2="91.44" y2="55.88" width="0.1524" layer="91"/> +<label x="73.66" y="55.88" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK0-TXLED" class="0"> +<segment> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="175.26" y1="127" x2="160.02" y2="127" width="0.1524" layer="91"/> +<label x="160.02" y="127" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE5/XCK1/MOSI"/> +<wire x1="68.58" y1="53.34" x2="91.44" y2="53.34" width="0.1524" layer="91"/> +<label x="73.66" y="53.34" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK0-TX" class="0"> +<segment> +<pinref part="J3" gate="G$1" pin="TX"/> +<wire x1="208.28" y1="152.4" x2="160.02" y2="152.4" width="0.1524" layer="91"/> +<label x="160.02" y="152.4" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE7/TXD1/SCK"/> +<wire x1="68.58" y1="48.26" x2="91.44" y2="48.26" width="0.1524" layer="91"/> +<label x="73.66" y="48.26" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK0-RX" class="0"> +<segment> +<pinref part="J3" gate="G$1" pin="RX"/> +<wire x1="208.28" y1="157.48" x2="160.02" y2="157.48" width="0.1524" layer="91"/> +<label x="160.02" y="157.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE6/RXD1/MISO"/> +<wire x1="68.58" y1="50.8" x2="91.44" y2="50.8" width="0.1524" layer="91"/> +<label x="73.66" y="50.8" size="1.778" layer="95"/> +</segment> +</net> +<net name="+3V3" class="0"> +<segment> +<pinref part="+3V2" gate="G$1" pin="+3V3"/> +<pinref part="J3" gate="G$1" pin="3V3"/> +<wire x1="182.88" y1="137.16" x2="208.28" y2="137.16" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="+3V3" gate="G$1" pin="+3V3"/> +<pinref part="J4" gate="G$1" pin="3V3"/> +<wire x1="182.88" y1="91.44" x2="208.28" y2="91.44" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="+3V4" gate="G$1" pin="+3V3"/> +<pinref part="J5" gate="G$1" pin="3V3"/> +<wire x1="182.88" y1="45.72" x2="208.28" y2="45.72" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="+3V5" gate="G$1" pin="+3V3"/> +<pinref part="J6" gate="G$1" pin="3V3"/> +<wire x1="182.88" y1="0" x2="208.28" y2="0" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="+3V6" gate="G$1" pin="+3V3"/> +<pinref part="J7" gate="G$1" pin="3V3"/> +<wire x1="182.88" y1="-45.72" x2="208.28" y2="-45.72" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="VCC"/> +<pinref part="C1" gate="G$1" pin="1"/> +<wire x1="17.78" y1="137.16" x2="5.08" y2="137.16" width="0.1524" layer="91"/> +<pinref part="C3" gate="G$1" pin="1"/> +<wire x1="5.08" y1="137.16" x2="-7.62" y2="137.16" width="0.1524" layer="91"/> +<junction x="5.08" y="137.16"/> +<pinref part="C4" gate="G$1" pin="1"/> +<wire x1="-7.62" y1="137.16" x2="-20.32" y2="137.16" width="0.1524" layer="91"/> +<junction x="-7.62" y="137.16"/> +<pinref part="C5" gate="G$1" pin="1"/> +<wire x1="-20.32" y1="137.16" x2="-33.02" y2="137.16" width="0.1524" layer="91"/> +<junction x="-20.32" y="137.16"/> +<pinref part="C6" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="137.16" x2="-45.72" y2="137.16" width="0.1524" layer="91"/> +<junction x="-33.02" y="137.16"/> +<wire x1="-45.72" y1="137.16" x2="-58.42" y2="137.16" width="0.1524" layer="91"/> +<junction x="-45.72" y="137.16"/> +<pinref part="U1" gate="G$1" pin="AVCC"/> +<wire x1="17.78" y1="142.24" x2="5.08" y2="142.24" width="0.1524" layer="91"/> +<wire x1="5.08" y1="142.24" x2="5.08" y2="137.16" width="0.1524" layer="91"/> +<pinref part="+3V8" gate="G$1" pin="+3V3"/> +</segment> +<segment> +<pinref part="J2" gate="G$1" pin="VCC"/> +<wire x1="-53.34" y1="152.4" x2="-58.42" y2="152.4" width="0.1524" layer="91"/> +<pinref part="+3V9" gate="G$1" pin="+3V3"/> +</segment> +<segment> +<pinref part="L1" gate="G$1" pin="1"/> +<pinref part="C2" gate="G$1" pin="1"/> +<wire x1="99.06" y1="182.88" x2="101.6" y2="182.88" width="0.1524" layer="91"/> +<pinref part="C9" gate="G$1" pin="1"/> +<wire x1="101.6" y1="182.88" x2="106.68" y2="182.88" width="0.1524" layer="91"/> +<wire x1="106.68" y1="182.88" x2="116.84" y2="182.88" width="0.1524" layer="91"/> +<junction x="106.68" y="182.88"/> +<pinref part="C10" gate="G$1" pin="1"/> +<wire x1="116.84" y1="182.88" x2="127" y2="182.88" width="0.1524" layer="91"/> +<junction x="116.84" y="182.88"/> +<pinref part="C11" gate="G$1" pin="1"/> +<wire x1="127" y1="182.88" x2="137.16" y2="182.88" width="0.1524" layer="91"/> +<junction x="127" y="182.88"/> +<wire x1="137.16" y1="182.88" x2="149.86" y2="182.88" width="0.1524" layer="91"/> +<junction x="137.16" y="182.88"/> +<wire x1="149.86" y1="182.88" x2="162.56" y2="182.88" width="0.1524" layer="91"/> +<wire x1="162.56" y1="182.88" x2="170.18" y2="182.88" width="0.1524" layer="91"/> +<wire x1="101.6" y1="182.88" x2="101.6" y2="175.26" width="0.1524" layer="91"/> +<junction x="101.6" y="182.88"/> +<pinref part="U2" gate="G$1" pin="FB"/> +<wire x1="101.6" y1="175.26" x2="68.58" y2="175.26" width="0.1524" layer="91"/> +<pinref part="+3V10" gate="G$1" pin="+3V3"/> +<pinref part="C15" gate="G$1" pin="1"/> +<junction x="149.86" y="182.88"/> +<pinref part="C16" gate="G$1" pin="1"/> +<junction x="162.56" y="182.88"/> +</segment> +<segment> +<wire x1="27.94" y1="271.78" x2="22.86" y2="271.78" width="0.1524" layer="91"/> +<wire x1="22.86" y1="271.78" x2="22.86" y2="264.16" width="0.1524" layer="91"/> +<wire x1="22.86" y1="264.16" x2="27.94" y2="264.16" width="0.1524" layer="91"/> +<wire x1="22.86" y1="264.16" x2="22.86" y2="256.54" width="0.1524" layer="91"/> +<junction x="22.86" y="264.16"/> +<wire x1="22.86" y1="256.54" x2="27.94" y2="256.54" width="0.1524" layer="91"/> +<wire x1="22.86" y1="264.16" x2="10.16" y2="264.16" width="0.1524" layer="91"/> +<pinref part="+3V11" gate="G$1" pin="+3V3"/> +<pinref part="C12" gate="G$1" pin="1"/> +<wire x1="10.16" y1="264.16" x2="0" y2="264.16" width="0.1524" layer="91"/> +<wire x1="0" y1="264.16" x2="-5.08" y2="264.16" width="0.1524" layer="91"/> +<wire x1="10.16" y1="259.08" x2="10.16" y2="264.16" width="0.1524" layer="91"/> +<junction x="10.16" y="264.16"/> +<pinref part="C13" gate="G$1" pin="1"/> +<wire x1="0" y1="259.08" x2="0" y2="264.16" width="0.1524" layer="91"/> +<junction x="0" y="264.16"/> +<pinref part="U4" gate="G$1" pin="VIO"/> +<pinref part="U4" gate="G$1" pin="VREGIN"/> +<pinref part="U4" gate="G$1" pin="VDD"/> +</segment> +<segment> +<pinref part="+3V12" gate="G$1" pin="+3V3"/> +<wire x1="147.32" y1="271.78" x2="144.78" y2="271.78" width="0.1524" layer="91"/> +<wire x1="144.78" y1="269.24" x2="144.78" y2="271.78" width="0.1524" layer="91"/> +<pinref part="D1" gate="G$1" pin="A"/> +<wire x1="121.92" y1="269.24" x2="144.78" y2="269.24" width="0.1524" layer="91"/> +<pinref part="D2" gate="G$1" pin="A"/> +<wire x1="134.62" y1="271.78" x2="144.78" y2="271.78" width="0.1524" layer="91"/> +<junction x="144.78" y="271.78"/> +</segment> +<segment> +<pinref part="D3" gate="G$1" pin="A"/> +<pinref part="+3V13" gate="G$1" pin="+3V3"/> +<wire x1="137.16" y1="200.66" x2="147.32" y2="200.66" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D4" gate="G$1" pin="A"/> +<pinref part="+3V14" gate="G$1" pin="+3V3"/> +<wire x1="137.16" y1="213.36" x2="147.32" y2="213.36" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="D5" gate="G$1" pin="A"/> +<pinref part="+3V15" gate="G$1" pin="+3V3"/> +<wire x1="137.16" y1="226.06" x2="147.32" y2="226.06" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R12" gate="G$1" pin="1"/> +<pinref part="+3V7" gate="G$1" pin="+3V3"/> +<wire x1="7.62" y1="223.52" x2="-5.08" y2="223.52" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<pinref part="J3" gate="G$1" pin="GND"/> +<pinref part="GND2" gate="1" pin="GND"/> +<wire x1="208.28" y1="142.24" x2="177.8" y2="142.24" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="J4" gate="G$1" pin="GND"/> +<pinref part="GND3" gate="1" pin="GND"/> +<wire x1="208.28" y1="96.52" x2="177.8" y2="96.52" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="J5" gate="G$1" pin="GND"/> +<pinref part="GND4" gate="1" pin="GND"/> +<wire x1="208.28" y1="50.8" x2="177.8" y2="50.8" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="J6" gate="G$1" pin="GND"/> +<pinref part="GND5" gate="1" pin="GND"/> +<wire x1="208.28" y1="5.08" x2="177.8" y2="5.08" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="J7" gate="G$1" pin="GND"/> +<pinref part="GND6" gate="1" pin="GND"/> +<wire x1="208.28" y1="-40.64" x2="177.8" y2="-40.64" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="GND"/> +<pinref part="C1" gate="G$1" pin="2"/> +<wire x1="17.78" y1="129.54" x2="5.08" y2="129.54" width="0.1524" layer="91"/> +<pinref part="C3" gate="G$1" pin="2"/> +<wire x1="5.08" y1="129.54" x2="-7.62" y2="129.54" width="0.1524" layer="91"/> +<junction x="5.08" y="129.54"/> +<pinref part="C4" gate="G$1" pin="2"/> +<wire x1="-7.62" y1="129.54" x2="-20.32" y2="129.54" width="0.1524" layer="91"/> +<junction x="-7.62" y="129.54"/> +<pinref part="C5" gate="G$1" pin="2"/> +<wire x1="-20.32" y1="129.54" x2="-33.02" y2="129.54" width="0.1524" layer="91"/> +<junction x="-20.32" y="129.54"/> +<pinref part="C6" gate="G$1" pin="2"/> +<wire x1="-33.02" y1="129.54" x2="-45.72" y2="129.54" width="0.1524" layer="91"/> +<junction x="-33.02" y="129.54"/> +<wire x1="-45.72" y1="129.54" x2="-58.42" y2="129.54" width="0.1524" layer="91"/> +<junction x="-45.72" y="129.54"/> +<pinref part="GND8" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="GND9" gate="1" pin="GND"/> +<pinref part="Y1" gate="G$1" pin="2"/> +<wire x1="-5.08" y1="91.44" x2="-2.54" y2="91.44" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="J2" gate="G$1" pin="GND"/> +<wire x1="-53.34" y1="157.48" x2="-55.88" y2="157.48" width="0.1524" layer="91"/> +<pinref part="S1" gate="G$1" pin="P1"/> +<wire x1="-33.02" y1="167.64" x2="-55.88" y2="167.64" width="0.1524" layer="91"/> +<wire x1="-55.88" y1="167.64" x2="-55.88" y2="157.48" width="0.1524" layer="91"/> +<wire x1="-55.88" y1="157.48" x2="-58.42" y2="157.48" width="0.1524" layer="91"/> +<junction x="-55.88" y="157.48"/> +<pinref part="GND10" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="X1" gate="G$1" pin="GND"/> +<pinref part="J13" gate="G$1" pin="POGO"/> +<wire x1="-63.5" y1="238.76" x2="-48.26" y2="238.76" width="0.1524" layer="91"/> +<pinref part="GND11" gate="1" pin="GND"/> +<wire x1="-35.56" y1="238.76" x2="-48.26" y2="238.76" width="0.1524" layer="91"/> +<junction x="-48.26" y="238.76"/> +</segment> +<segment> +<pinref part="U2" gate="G$1" pin="GND"/> +<wire x1="38.1" y1="175.26" x2="30.48" y2="175.26" width="0.1524" layer="91"/> +<wire x1="30.48" y1="175.26" x2="30.48" y2="172.72" width="0.1524" layer="91"/> +<pinref part="U2" gate="G$1" pin="PGND"/> +<wire x1="30.48" y1="172.72" x2="38.1" y2="172.72" width="0.1524" layer="91"/> +<wire x1="30.48" y1="172.72" x2="22.86" y2="172.72" width="0.1524" layer="91"/> +<junction x="30.48" y="172.72"/> +<pinref part="GND12" gate="1" pin="GND"/> +<pinref part="U$1" gate="G$1" pin="1"/> +<wire x1="22.86" y1="172.72" x2="20.32" y2="172.72" width="0.1524" layer="91"/> +<wire x1="25.4" y1="182.88" x2="22.86" y2="182.88" width="0.1524" layer="91"/> +<wire x1="22.86" y1="182.88" x2="22.86" y2="172.72" width="0.1524" layer="91"/> +<junction x="22.86" y="172.72"/> +</segment> +<segment> +<pinref part="GND13" gate="1" pin="GND"/> +<pinref part="C8" gate="G$1" pin="1"/> +<wire x1="33.02" y1="205.74" x2="33.02" y2="203.2" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C2" gate="G$1" pin="2"/> +<pinref part="C9" gate="G$1" pin="2"/> +<wire x1="106.68" y1="175.26" x2="116.84" y2="175.26" width="0.1524" layer="91"/> +<pinref part="C10" gate="G$1" pin="2"/> +<wire x1="116.84" y1="175.26" x2="127" y2="175.26" width="0.1524" layer="91"/> +<junction x="116.84" y="175.26"/> +<pinref part="C11" gate="G$1" pin="2"/> +<wire x1="127" y1="175.26" x2="137.16" y2="175.26" width="0.1524" layer="91"/> +<junction x="127" y="175.26"/> +<wire x1="137.16" y1="175.26" x2="149.86" y2="175.26" width="0.1524" layer="91"/> +<junction x="137.16" y="175.26"/> +<pinref part="GND14" gate="1" pin="GND"/> +<pinref part="C15" gate="G$1" pin="2"/> +<wire x1="149.86" y1="175.26" x2="162.56" y2="175.26" width="0.1524" layer="91"/> +<junction x="149.86" y="175.26"/> +<pinref part="C16" gate="G$1" pin="2"/> +<wire x1="162.56" y1="175.26" x2="170.18" y2="175.26" width="0.1524" layer="91"/> +<junction x="162.56" y="175.26"/> +</segment> +<segment> +<wire x1="27.94" y1="248.92" x2="10.16" y2="248.92" width="0.1524" layer="91"/> +<pinref part="GND15" gate="1" pin="GND"/> +<pinref part="C12" gate="G$1" pin="2"/> +<wire x1="10.16" y1="248.92" x2="0" y2="248.92" width="0.1524" layer="91"/> +<wire x1="0" y1="248.92" x2="-5.08" y2="248.92" width="0.1524" layer="91"/> +<wire x1="10.16" y1="251.46" x2="10.16" y2="248.92" width="0.1524" layer="91"/> +<junction x="10.16" y="248.92"/> +<pinref part="C13" gate="G$1" pin="2"/> +<wire x1="0" y1="251.46" x2="0" y2="248.92" width="0.1524" layer="91"/> +<junction x="0" y="248.92"/> +<pinref part="U4" gate="G$1" pin="GND"/> +</segment> +<segment> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="114.3" y1="200.66" x2="99.06" y2="200.66" width="0.1524" layer="91"/> +<pinref part="GND17" gate="1" pin="GND"/> +</segment> +</net> +<net name="ATK1-RX" class="0"> +<segment> +<pinref part="J4" gate="G$1" pin="RX"/> +<wire x1="208.28" y1="111.76" x2="160.02" y2="111.76" width="0.1524" layer="91"/> +<label x="160.02" y="111.76" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE2/RXD0"/> +<wire x1="68.58" y1="60.96" x2="91.44" y2="60.96" width="0.1524" layer="91"/> +<label x="73.66" y="60.96" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK1-TX" class="0"> +<segment> +<pinref part="J4" gate="G$1" pin="TX"/> +<wire x1="208.28" y1="106.68" x2="160.02" y2="106.68" width="0.1524" layer="91"/> +<label x="160.02" y="106.68" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE3/TXD0"/> +<wire x1="68.58" y1="58.42" x2="91.44" y2="58.42" width="0.1524" layer="91"/> +<label x="73.66" y="58.42" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK1-RXLED" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="1"/> +<wire x1="187.96" y1="86.36" x2="160.02" y2="86.36" width="0.1524" layer="91"/> +<label x="160.02" y="86.36" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE0/SDA"/> +<wire x1="68.58" y1="66.04" x2="91.44" y2="66.04" width="0.1524" layer="91"/> +<label x="73.66" y="66.04" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK1-TXLED" class="0"> +<segment> +<pinref part="R5" gate="G$1" pin="1"/> +<wire x1="175.26" y1="81.28" x2="160.02" y2="81.28" width="0.1524" layer="91"/> +<label x="160.02" y="81.28" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PE1/SCL/XCK0"/> +<wire x1="68.58" y1="63.5" x2="91.44" y2="63.5" width="0.1524" layer="91"/> +<label x="73.66" y="63.5" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK2-RX" class="0"> +<segment> +<pinref part="J5" gate="G$1" pin="RX"/> +<wire x1="208.28" y1="66.04" x2="160.02" y2="66.04" width="0.1524" layer="91"/> +<label x="160.02" y="66.04" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD6/RXD1/MISO/D-"/> +<wire x1="68.58" y1="73.66" x2="91.44" y2="73.66" width="0.1524" layer="91"/> +<label x="73.66" y="73.66" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK2-TX" class="0"> +<segment> +<pinref part="J5" gate="G$1" pin="TX"/> +<wire x1="208.28" y1="60.96" x2="160.02" y2="60.96" width="0.1524" layer="91"/> +<label x="160.02" y="60.96" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD7/TXD1/SCK/D+"/> +<wire x1="68.58" y1="71.12" x2="91.44" y2="71.12" width="0.1524" layer="91"/> +<label x="73.66" y="71.12" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK2-RXLED" class="0"> +<segment> +<pinref part="R6" gate="G$1" pin="1"/> +<wire x1="187.96" y1="40.64" x2="160.02" y2="40.64" width="0.1524" layer="91"/> +<label x="160.02" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD4/SS"/> +<wire x1="68.58" y1="78.74" x2="91.44" y2="78.74" width="0.1524" layer="91"/> +<label x="73.66" y="78.74" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK2-TXLED" class="0"> +<segment> +<pinref part="R7" gate="G$1" pin="1"/> +<wire x1="175.26" y1="35.56" x2="160.02" y2="35.56" width="0.1524" layer="91"/> +<label x="160.02" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD5/XCK/MOSI"/> +<wire x1="68.58" y1="76.2" x2="91.44" y2="76.2" width="0.1524" layer="91"/> +<label x="73.66" y="76.2" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK3-RX" class="0"> +<segment> +<pinref part="J6" gate="G$1" pin="RX"/> +<wire x1="208.28" y1="20.32" x2="160.02" y2="20.32" width="0.1524" layer="91"/> +<label x="160.02" y="20.32" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD2/RXD0"/> +<wire x1="68.58" y1="83.82" x2="91.44" y2="83.82" width="0.1524" layer="91"/> +<label x="73.66" y="83.82" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK3-TX" class="0"> +<segment> +<pinref part="J6" gate="G$1" pin="TX"/> +<wire x1="208.28" y1="15.24" x2="160.02" y2="15.24" width="0.1524" layer="91"/> +<label x="160.02" y="15.24" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD3/TXD0"/> +<wire x1="68.58" y1="81.28" x2="91.44" y2="81.28" width="0.1524" layer="91"/> +<label x="73.66" y="81.28" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK3-RXLED" class="0"> +<segment> +<pinref part="R8" gate="G$1" pin="1"/> +<wire x1="187.96" y1="-5.08" x2="160.02" y2="-5.08" width="0.1524" layer="91"/> +<label x="160.02" y="-5.08" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD0"/> +<wire x1="68.58" y1="88.9" x2="91.44" y2="88.9" width="0.1524" layer="91"/> +<label x="73.66" y="88.9" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK3-TXLED" class="0"> +<segment> +<pinref part="R9" gate="G$1" pin="1"/> +<wire x1="175.26" y1="-10.16" x2="160.02" y2="-10.16" width="0.1524" layer="91"/> +<label x="160.02" y="-10.16" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PD1/XCK0"/> +<wire x1="68.58" y1="86.36" x2="91.44" y2="86.36" width="0.1524" layer="91"/> +<label x="73.66" y="86.36" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK4-RX" class="0"> +<segment> +<pinref part="J7" gate="G$1" pin="RX"/> +<wire x1="208.28" y1="-25.4" x2="160.02" y2="-25.4" width="0.1524" layer="91"/> +<label x="160.02" y="-25.4" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PC6/RXD1/MISO"/> +<wire x1="68.58" y1="96.52" x2="91.44" y2="96.52" width="0.1524" layer="91"/> +<label x="73.66" y="96.52" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK4-TX" class="0"> +<segment> +<pinref part="J7" gate="G$1" pin="TX"/> +<wire x1="208.28" y1="-30.48" x2="160.02" y2="-30.48" width="0.1524" layer="91"/> +<label x="160.02" y="-30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PC7/TXD1/SCK"/> +<wire x1="68.58" y1="93.98" x2="91.44" y2="93.98" width="0.1524" layer="91"/> +<label x="73.66" y="93.98" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK4-RXLED" class="0"> +<segment> +<pinref part="R10" gate="G$1" pin="1"/> +<wire x1="187.96" y1="-50.8" x2="160.02" y2="-50.8" width="0.1524" layer="91"/> +<label x="160.02" y="-50.8" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PC4/SS"/> +<wire x1="68.58" y1="101.6" x2="91.44" y2="101.6" width="0.1524" layer="91"/> +<label x="73.66" y="101.6" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK4-TXLED" class="0"> +<segment> +<pinref part="R11" gate="G$1" pin="1"/> +<wire x1="175.26" y1="-55.88" x2="160.02" y2="-55.88" width="0.1524" layer="91"/> +<label x="160.02" y="-55.88" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PC5/XCK1/MOSI"/> +<wire x1="68.58" y1="99.06" x2="91.44" y2="99.06" width="0.1524" layer="91"/> +<label x="73.66" y="99.06" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK0-CLKIN" class="0"> +<segment> +<pinref part="J3" gate="G$1" pin="CLKIN"/> +<wire x1="208.28" y1="162.56" x2="160.02" y2="162.56" width="0.1524" layer="91"/> +<label x="160.02" y="162.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PF5"/> +<wire x1="68.58" y1="30.48" x2="91.44" y2="30.48" width="0.1524" layer="91"/> +<label x="73.66" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK1-CLKIN" class="0"> +<segment> +<pinref part="J4" gate="G$1" pin="CLKIN"/> +<wire x1="208.28" y1="116.84" x2="160.02" y2="116.84" width="0.1524" layer="91"/> +<label x="160.02" y="116.84" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PF4"/> +<wire x1="68.58" y1="33.02" x2="91.44" y2="33.02" width="0.1524" layer="91"/> +<label x="73.66" y="33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK2-CLKIN" class="0"> +<segment> +<pinref part="J5" gate="G$1" pin="CLKIN"/> +<wire x1="208.28" y1="71.12" x2="160.02" y2="71.12" width="0.1524" layer="91"/> +<label x="160.02" y="71.12" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PF3/TXD0"/> +<wire x1="68.58" y1="35.56" x2="91.44" y2="35.56" width="0.1524" layer="91"/> +<label x="73.66" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK3-CLKIN" class="0"> +<segment> +<pinref part="J6" gate="G$1" pin="CLKIN"/> +<wire x1="208.28" y1="25.4" x2="160.02" y2="25.4" width="0.1524" layer="91"/> +<label x="160.02" y="25.4" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PF2/RXD0"/> +<wire x1="68.58" y1="38.1" x2="91.44" y2="38.1" width="0.1524" layer="91"/> +<label x="73.66" y="38.1" size="1.778" layer="95"/> +</segment> +</net> +<net name="ATK4-CLKIN" class="0"> +<segment> +<pinref part="J7" gate="G$1" pin="CLKIN"/> +<wire x1="208.28" y1="-20.32" x2="160.02" y2="-20.32" width="0.1524" layer="91"/> +<label x="160.02" y="-20.32" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PF1/XCK0"/> +<wire x1="68.58" y1="40.64" x2="91.44" y2="40.64" width="0.1524" layer="91"/> +<label x="73.66" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="PDI_DATA" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="PDI_DATA"/> +<label x="-2.54" y="152.4" size="1.778" layer="95"/> +<pinref part="J2" gate="G$1" pin="PDI_DATA"/> +<wire x1="17.78" y1="152.4" x2="-22.86" y2="152.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="RESET/PDI_CLK" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="RESET/PDI_CLK"/> +<label x="-2.54" y="157.48" size="1.778" layer="95"/> +<pinref part="J2" gate="G$1" pin="PDI_CLK"/> +<wire x1="-22.86" y1="157.48" x2="-17.78" y2="157.48" width="0.1524" layer="91"/> +<pinref part="S1" gate="G$1" pin="S1"/> +<wire x1="-17.78" y1="157.48" x2="17.78" y2="157.48" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="167.64" x2="-17.78" y2="167.64" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="167.64" x2="-17.78" y2="157.48" width="0.1524" layer="91"/> +<junction x="-17.78" y="157.48"/> +</segment> +</net> +<net name="N$13" class="0"> +<segment> +<pinref part="Y1" gate="G$1" pin="1"/> +<pinref part="U1" gate="G$1" pin="PR0/XTAL2"/> +<wire x1="5.08" y1="99.06" x2="17.78" y2="99.06" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$14" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="PR1/XTAL1"/> +<pinref part="Y1" gate="G$1" pin="3"/> +<wire x1="17.78" y1="83.82" x2="5.08" y2="83.82" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VUSB" class="0"> +<segment> +<pinref part="X1" gate="G$1" pin="VBUS"/> +<label x="-55.88" y="236.22" size="1.778" layer="95"/> +<wire x1="-63.5" y1="236.22" x2="-22.86" y2="236.22" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="236.22" x2="20.32" y2="236.22" width="0.1524" layer="91"/> +<wire x1="20.32" y1="236.22" x2="20.32" y2="241.3" width="0.1524" layer="91"/> +<wire x1="20.32" y1="241.3" x2="27.94" y2="241.3" width="0.1524" layer="91"/> +<pinref part="J10" gate="G$1" pin="POGO"/> +<junction x="-22.86" y="236.22"/> +<pinref part="U4" gate="G$1" pin="VBUS"/> +</segment> +<segment> +<pinref part="U2" gate="G$1" pin="VCC"/> +<label x="25.4" y="190.5" size="1.778" layer="95"/> +<pinref part="C8" gate="G$1" pin="2"/> +<wire x1="33.02" y1="190.5" x2="38.1" y2="190.5" width="0.1524" layer="91"/> +<wire x1="33.02" y1="190.5" x2="33.02" y2="195.58" width="0.1524" layer="91"/> +<wire x1="33.02" y1="190.5" x2="25.4" y2="190.5" width="0.1524" layer="91"/> +<junction x="33.02" y="190.5"/> +</segment> +</net> +<net name="DM" class="0"> +<segment> +<pinref part="X1" gate="G$1" pin="D-"/> +<pinref part="J12" gate="G$1" pin="POGO"/> +<wire x1="-63.5" y1="233.68" x2="-35.56" y2="233.68" width="0.1524" layer="91"/> +<label x="-55.88" y="233.68" size="1.778" layer="95"/> +<wire x1="-35.56" y1="233.68" x2="27.94" y2="233.68" width="0.1524" layer="91"/> +<junction x="-35.56" y="233.68"/> +<pinref part="U4" gate="G$1" pin="DM"/> +</segment> +</net> +<net name="DP" class="0"> +<segment> +<pinref part="X1" gate="G$1" pin="D+"/> +<pinref part="J11" gate="G$1" pin="POGO"/> +<wire x1="-63.5" y1="231.14" x2="-48.26" y2="231.14" width="0.1524" layer="91"/> +<label x="-55.88" y="231.14" size="1.778" layer="95"/> +<wire x1="-48.26" y1="231.14" x2="27.94" y2="231.14" width="0.1524" layer="91"/> +<junction x="-48.26" y="231.14"/> +<pinref part="U4" gate="G$1" pin="DP"/> +</segment> +</net> +<net name="N$20" class="0"> +<segment> +<pinref part="U2" gate="G$1" pin="BST"/> +<pinref part="C7" gate="G$1" pin="1"/> +<wire x1="68.58" y1="190.5" x2="73.66" y2="190.5" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VSW" class="0"> +<segment> +<pinref part="U2" gate="G$1" pin="VSW"/> +<pinref part="C7" gate="G$1" pin="2"/> +<wire x1="68.58" y1="182.88" x2="73.66" y2="182.88" width="0.1524" layer="91"/> +<pinref part="L1" gate="G$1" pin="2"/> +<wire x1="73.66" y1="182.88" x2="83.82" y2="182.88" width="0.1524" layer="91"/> +<junction x="73.66" y="182.88"/> +</segment> +</net> +<net name="CPRX" class="0"> +<segment> +<wire x1="68.58" y1="233.68" x2="83.82" y2="233.68" width="0.1524" layer="91"/> +<label x="73.66" y="233.68" size="1.778" layer="95"/> +<pinref part="U4" gate="G$1" pin="TXD"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PC2/RXD0"/> +<wire x1="68.58" y1="106.68" x2="91.44" y2="106.68" width="0.1524" layer="91"/> +<label x="73.66" y="106.68" size="1.778" layer="95"/> +</segment> +</net> +<net name="CPTX" class="0"> +<segment> +<wire x1="68.58" y1="231.14" x2="83.82" y2="231.14" width="0.1524" layer="91"/> +<label x="73.66" y="231.14" size="1.778" layer="95"/> +<pinref part="U4" gate="G$1" pin="RXD"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PC3/TXD0"/> +<wire x1="68.58" y1="104.14" x2="91.44" y2="104.14" width="0.1524" layer="91"/> +<label x="73.66" y="104.14" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$19" class="0"> +<segment> +<wire x1="27.94" y1="223.52" x2="17.78" y2="223.52" width="0.1524" layer="91"/> +<pinref part="U4" gate="G$1" pin="RST_"/> +<pinref part="R12" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$34" class="0"> +<segment> +<pinref part="U$1" gate="G$1" pin="2"/> +<pinref part="U2" gate="G$1" pin="EN"/> +<wire x1="35.56" y1="182.88" x2="38.1" y2="182.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="CPTXLED" class="0"> +<segment> +<pinref part="R15" gate="G$1" pin="1"/> +<wire x1="68.58" y1="271.78" x2="99.06" y2="271.78" width="0.1524" layer="91"/> +<label x="71.12" y="271.78" size="1.778" layer="95"/> +<pinref part="U4" gate="G$1" pin="GPIO0/TXT"/> +</segment> +</net> +<net name="CPRXLED" class="0"> +<segment> +<pinref part="R14" gate="G$1" pin="1"/> +<wire x1="86.36" y1="269.24" x2="68.58" y2="269.24" width="0.1524" layer="91"/> +<label x="71.12" y="269.24" size="1.778" layer="95"/> +<pinref part="U4" gate="G$1" pin="GPIO1/RXT"/> +</segment> +</net> +<net name="N$37" class="0"> +<segment> +<pinref part="R14" gate="G$1" pin="2"/> +<pinref part="D1" gate="G$1" pin="C"/> +<wire x1="96.52" y1="269.24" x2="114.3" y2="269.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$38" class="0"> +<segment> +<pinref part="R15" gate="G$1" pin="2"/> +<pinref part="D2" gate="G$1" pin="C"/> +<wire x1="109.22" y1="271.78" x2="127" y2="271.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$15" class="0"> +<segment> +<pinref part="D3" gate="G$1" pin="C"/> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="129.54" y1="200.66" x2="124.46" y2="200.66" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$17" class="0"> +<segment> +<pinref part="D4" gate="G$1" pin="C"/> +<pinref part="R16" gate="G$1" pin="2"/> +<wire x1="129.54" y1="213.36" x2="124.46" y2="213.36" width="0.1524" layer="91"/> +</segment> +</net> +<net name="STLCLK" class="0"> +<segment> +<pinref part="R16" gate="G$1" pin="1"/> +<wire x1="114.3" y1="213.36" x2="99.06" y2="213.36" width="0.1524" layer="91"/> +<label x="99.06" y="213.36" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PA0/AREF"/> +<wire x1="68.58" y1="157.48" x2="91.44" y2="157.48" width="0.1524" layer="91"/> +<label x="73.66" y="157.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$21" class="0"> +<segment> +<pinref part="D5" gate="G$1" pin="C"/> +<pinref part="R17" gate="G$1" pin="2"/> +<wire x1="129.54" y1="226.06" x2="124.46" y2="226.06" width="0.1524" layer="91"/> +</segment> +</net> +<net name="STLERR" class="0"> +<segment> +<pinref part="R17" gate="G$1" pin="1"/> +<wire x1="114.3" y1="226.06" x2="99.06" y2="226.06" width="0.1524" layer="91"/> +<label x="99.06" y="226.06" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PA1"/> +<wire x1="68.58" y1="154.94" x2="91.44" y2="154.94" width="0.1524" layer="91"/> +<label x="73.66" y="154.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="R2" gate="G$1" pin="2"/> +<pinref part="J3" gate="G$1" pin="GRN-RX"/> +<wire x1="198.12" y1="132.08" x2="208.28" y2="132.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="J3" gate="G$1" pin="YLW-TX"/> +<pinref part="R3" gate="G$1" pin="2"/> +<wire x1="208.28" y1="127" x2="185.42" y2="127" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="R4" gate="G$1" pin="2"/> +<pinref part="J4" gate="G$1" pin="GRN-RX"/> +<wire x1="198.12" y1="86.36" x2="208.28" y2="86.36" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="J4" gate="G$1" pin="YLW-TX"/> +<pinref part="R5" gate="G$1" pin="2"/> +<wire x1="208.28" y1="81.28" x2="185.42" y2="81.28" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="R6" gate="G$1" pin="2"/> +<pinref part="J5" gate="G$1" pin="GRN-RX"/> +<wire x1="198.12" y1="40.64" x2="208.28" y2="40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$6" class="0"> +<segment> +<pinref part="J5" gate="G$1" pin="YLW-TX"/> +<pinref part="R7" gate="G$1" pin="2"/> +<wire x1="208.28" y1="35.56" x2="185.42" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$7" class="0"> +<segment> +<pinref part="R8" gate="G$1" pin="2"/> +<pinref part="J6" gate="G$1" pin="GRN-RX"/> +<wire x1="198.12" y1="-5.08" x2="208.28" y2="-5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$8" class="0"> +<segment> +<pinref part="J6" gate="G$1" pin="YLW-TX"/> +<pinref part="R9" gate="G$1" pin="2"/> +<wire x1="208.28" y1="-10.16" x2="185.42" y2="-10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$9" class="0"> +<segment> +<pinref part="R10" gate="G$1" pin="2"/> +<pinref part="J7" gate="G$1" pin="GRN-RX"/> +<wire x1="198.12" y1="-50.8" x2="208.28" y2="-50.8" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$10" class="0"> +<segment> +<pinref part="J7" gate="G$1" pin="YLW-TX"/> +<pinref part="R11" gate="G$1" pin="2"/> +<wire x1="208.28" y1="-55.88" x2="185.42" y2="-55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="ATK-CLKOUT" class="0"> +<segment> +<pinref part="J3" gate="G$1" pin="CLKOUT"/> +<wire x1="208.28" y1="147.32" x2="160.02" y2="147.32" width="0.1524" layer="91"/> +<label x="160.02" y="147.32" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="J4" gate="G$1" pin="CLKOUT"/> +<wire x1="208.28" y1="101.6" x2="160.02" y2="101.6" width="0.1524" layer="91"/> +<label x="160.02" y="101.6" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="J5" gate="G$1" pin="CLKOUT"/> +<wire x1="208.28" y1="55.88" x2="160.02" y2="55.88" width="0.1524" layer="91"/> +<label x="160.02" y="55.88" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="J6" gate="G$1" pin="CLKOUT"/> +<wire x1="208.28" y1="10.16" x2="160.02" y2="10.16" width="0.1524" layer="91"/> +<label x="160.02" y="10.16" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="J7" gate="G$1" pin="CLKOUT"/> +<wire x1="208.28" y1="-35.56" x2="160.02" y2="-35.56" width="0.1524" layer="91"/> +<label x="160.02" y="-35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="PF0"/> +<wire x1="68.58" y1="43.18" x2="91.44" y2="43.18" width="0.1524" layer="91"/> +<label x="73.66" y="43.18" size="1.778" layer="95"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +<compatibility> +<note version="8.2" severity="warning"> +Since Version 8.2, EAGLE supports online libraries. The ids +of those online libraries will not be understood (or retained) +with this version. +</note> +<note version="8.3" severity="warning"> +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. +</note> +</compatibility> +</eagle> diff --git a/circuit/atkrouter-v01/atkrouter-v01_2018-06-08.zip b/circuit/atkrouter-v01/atkrouter-v01_2018-06-08.zip new file mode 100644 index 0000000000000000000000000000000000000000..e33c9d0fcc5f15d31e9d52524dba00e16fee2a8e Binary files /dev/null and b/circuit/atkrouter-v01/atkrouter-v01_2018-06-08.zip differ diff --git a/circuit/atkrouter-v01/eagle.epf b/circuit/atkrouter-v01/eagle.epf new file mode 100644 index 0000000000000000000000000000000000000000..f414bc7410f1e0c6fe6bbb27f271f064e3c69534 --- /dev/null +++ b/circuit/atkrouter-v01/eagle.epf @@ -0,0 +1,137 @@ +[Eagle] +Version="09 00 00" +Platform="Windows" +Globals="Globals" +Desktop="Desktop" + +[Globals] +AutoSaveProject=1 +UsedLibraryUrn="urn:adsk.eagle:library:217" +UsedLibraryUrn="urn:adsk.eagle:library:325" +UsedLibraryUrn="urn:adsk.eagle:library:371" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/connector.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/fab.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/lights.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/microcontrollers.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/motors.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/passives.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/power.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries/eagle/sensor.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries_jake/eagle/sparkfun/SparkFun-Connectors.lbr" +UsedLibrary="D:/Dropbox (Personal)/CBA/doc/libraries_jake/eagle/jake/tag-connect-2050.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/Comparators.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/Digital.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/FilterProducts.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/Misc.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/Opamps.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/Optos.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/PAsystem.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/PowerProducts.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/References.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/SpecialFunctions.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/capmeter.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/diode.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/lt-spice-simulation.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/lt-supply.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/rload.lbr" +UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/sym.lbr" + +[Win_1] +Type="Board Editor" +Number=3 +File="atkrouter-v01.brd" +View="-5.94496 21.7574 107.847 82.1959" +WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.4064 0.6096 0.8128 1.27 2.54 0.508 0.254 0.3048 1.016 0.1524" +PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6" +ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0" +ViaDrills=" 0.2 0.25 0.4 0.5 0.6 0.7 0.75 0.8 0.85 0.9 1 0.35 0.55 0.45 0.65 0.3" +HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" +TextSizes=" 0.254 0.3048 0.4064 0.6096 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778 0.8128" +PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27" +PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0" +DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13" +DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0" +DimensionExtLengths=" 1.27 2.54 1 2 3 0" +DimensionExtOffsets=" 1.27 2.54 1 2 3 0" +SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635" +WireBend=1 +WireBendSet=0 +WireCap=1 +MiterStyle=0 +PadShape=0 +ViaShape=1 +PolygonPour=0 +PolygonRank=1 +PolygonThermals=1 +PolygonOrphans=0 +TextRatio=8 +DimensionUnit=1 +DimensionPrecision=2 +DimensionShowUnit=0 +PinDirection=3 +PinFunction=0 +PinLength=2 +PinVisible=3 +SwapLevel=0 +ArcDirection=0 +AddLevel=2 +PadsSameType=0 +Layer=48 + +[Win_2] +Type="Schematic Editor" +Number=1 +File="atkrouter-v01.sch" +View="-58.1526 -5.84485 208.12 165.332" +WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524" +PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6" +ViaDiameters=" 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.3 0" +ViaDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" +HoleDrills=" 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1 0.35" +TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778" +PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27" +PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" +MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0" +DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13" +DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0" +DimensionExtLengths=" 1.27 2.54 1 2 3 0" +DimensionExtOffsets=" 1.27 2.54 1 2 3 0" +SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635" +WireBend=4 +WireBendSet=31 +WireCap=1 +MiterStyle=0 +PadShape=0 +ViaShape=1 +PolygonPour=0 +PolygonRank=0 +PolygonThermals=1 +PolygonOrphans=0 +TextRatio=8 +DimensionUnit=1 +DimensionPrecision=2 +DimensionShowUnit=0 +PinDirection=3 +PinFunction=0 +PinLength=2 +PinVisible=3 +SwapLevel=0 +ArcDirection=0 +AddLevel=2 +PadsSameType=0 +Layer=91 +Views=" 1: -58.1526 -5.84485 208.12 165.332" +Sheet="1" + +[Win_3] +Type="Control Panel" +Number=0 + +[Desktop] +Screen="3840 1080" +Window="Win_1" +Window="Win_2" +Window="Win_3" diff --git a/circuit/mkrouter-v06/eagle.epf b/circuit/mkrouter-v06/eagle.epf index 47067fa240a539049ffa9fe57d0eb6b24e3ae1ee..5dc995a2acbd8e6bdcb84d52bee5f9a2d97db876 100644 --- a/circuit/mkrouter-v06/eagle.epf +++ b/circuit/mkrouter-v06/eagle.epf @@ -70,7 +70,7 @@ Package="RASPBERRYPI-3BPLUS" Type="Schematic Editor" Number=1 File="mkrouter-v06.sch" -View="18.324 124.475 115.773 217.342" +View="-39.971 209.905 100.356 343.634" WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524" PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6" @@ -109,14 +109,14 @@ ArcDirection=0 AddLevel=2 PadsSameType=0 Layer=91 -Views=" 1: 18.324 124.475 115.773 217.342" +Views=" 1: -39.971 209.905 100.356 343.634" Sheet="1" [Win_3] Type="Board Editor" Number=2 File="mkrouter-v06.brd" -View="70.3133 23.0011 136.121 116.552" +View="13.4326 60.5944 28.7374 82.3514" WireWidths=" 0.0762 0.1016 0.127 0.15 0.4064 0.508 0.6096 2.54 0.2 0.254 0.2032 0.3048 1.27 1.016 0.8128 0.1524" PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0" PadDrills=" 0.2 0.25 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6 0.3" diff --git a/datasheet/cp2102n-datasheet.pdf b/datasheet/cp2102n-datasheet.pdf new file mode 100644 index 0000000000000000000000000000000000000000..4d693e7f4e77e00d3086b6cb9e72669abf93eafc Binary files /dev/null and b/datasheet/cp2102n-datasheet.pdf differ diff --git a/embedded/README.md b/embedded/README.md index 552e7a4b67009390a0802c71fb911af62a35348a..70ba3dfeb10f26b160e570b9600fbe921bb2c5a0 100644 --- a/embedded/README.md +++ b/embedded/README.md @@ -1,17 +1,7 @@ -# Programming the Router +# AutomataKit Router Firmware Notes -running on code from tinynet... +Firmware for the board follows the [automatakit](https://gitlab.cba.mit.edu/jakeread/automatakit) architecture, and is available here for perusal. -finding lock bit issue? +Communication is handled asynchronously: bytes received on the UART are loaded into a ringbuffer, where they are later parsed in to packets. Parsing happens as oven as possible. -setting that does nothing - -so, likely that clock is configured incorrectly - will try using erase jumper - -changing config from pllack to 8m_rc might have fixed this - -some abortive work here trying to get the usb cdc example working again - I've become convinced again that I can and should do this. However, after a few brief moments bringin the example code up and configuring my clocks properly (and generally going abobut this with a more level head) I realize that the version of this board I'm currently debugging doesn't have USB DM / DP lines routed :'( haha so I'll wait until the new version arrives - -http://asf.atmel.com/docs/latest/uc3l/html/udi_cdc_quickstart.html#udi_cdc_use_cases - -but I started a new atmel studio project for this, so it shouldn't be too hard to hop back in later \ No newline at end of file +... \ No newline at end of file diff --git a/embedded/atkrouter/.vs/atkrouter/v14/.atsuo b/embedded/atkrouter/.vs/atkrouter/v14/.atsuo new file mode 100644 index 0000000000000000000000000000000000000000..dda766cbda3e1df81cbb5ab604dddf255fa0b9bf Binary files /dev/null and b/embedded/atkrouter/.vs/atkrouter/v14/.atsuo differ diff --git a/embedded/atkrouter/atkrouter.atsln b/embedded/atkrouter/atkrouter.atsln new file mode 100644 index 0000000000000000000000000000000000000000..e3e647f944c02941f541fddd28da21f2c438420e --- /dev/null +++ b/embedded/atkrouter/atkrouter.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "atkrouter", "atkrouter\atkrouter.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|AVR = Debug|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.ActiveCfg = Debug|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.Build.0 = Debug|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.ActiveCfg = Release|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/embedded/atkrouter/atkrouter/Debug/Makefile b/embedded/atkrouter/atkrouter/Debug/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..40467e4329d1e115b861da1065f21ab1b6c3e232 --- /dev/null +++ b/embedded/atkrouter/atkrouter/Debug/Makefile @@ -0,0 +1,171 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL := cmd.exe +RM := rm -rf + +USER_OBJS := + +LIBS := +PROJ := + +O_SRCS := +C_SRCS := +S_SRCS := +S_UPPER_SRCS := +OBJ_SRCS := +ASM_SRCS := +PREPROCESSING_SRCS := +OBJS := +OBJS_AS_ARGS := +C_DEPS := +C_DEPS_AS_ARGS := +EXECUTABLES := +OUTPUT_FILE_PATH := +OUTPUT_FILE_PATH_AS_ARGS := +AVR_APP_PATH :=$$$AVR_APP_PATH$$$ +QUOTE := " +ADDITIONAL_DEPENDENCIES:= +OUTPUT_FILE_DEP:= +LIB_DEP:= +LINKER_SCRIPT_DEP:= + +# Every subdirectory with source files must be described here +SUBDIRS := + + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../atkhandler.c \ +../atkport.c \ +../fastmath.c \ +../main.c \ +../pin.c \ +../ringbuffer.c \ +../uartport.c + + +PREPROCESSING_SRCS += + + +ASM_SRCS += + + +OBJS += \ +atkhandler.o \ +atkport.o \ +fastmath.o \ +main.o \ +pin.o \ +ringbuffer.o \ +uartport.o + +OBJS_AS_ARGS += \ +atkhandler.o \ +atkport.o \ +fastmath.o \ +main.o \ +pin.o \ +ringbuffer.o \ +uartport.o + +C_DEPS += \ +atkhandler.d \ +atkport.d \ +fastmath.d \ +main.d \ +pin.d \ +ringbuffer.d \ +uartport.d + +C_DEPS_AS_ARGS += \ +atkhandler.d \ +atkport.d \ +fastmath.d \ +main.d \ +pin.d \ +ringbuffer.d \ +uartport.d + +OUTPUT_FILE_PATH +=atkrouter.elf + +OUTPUT_FILE_PATH_AS_ARGS +=atkrouter.elf + +ADDITIONAL_DEPENDENCIES:= + +OUTPUT_FILE_DEP:= ./makedep.mk + +LIB_DEP+= + +LINKER_SCRIPT_DEP+= + + +# AVR32/GNU C Compiler + + + + + + + + + + + + + + + +./%.o: .././%.c + @echo Building file: $< + @echo Invoking: AVR/GNU C Compiler : 5.4.0 + $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAA_DFP\1.1.68\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega256a3u -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAA_DFP\1.1.68\gcc\dev\atxmega256a3u" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + + + +# AVR32/GNU Preprocessing Assembler + + + +# AVR32/GNU Assembler + + + + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) + +$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) + @echo Building target: $@ + @echo Invoking: AVR/GNU Linker : 5.4.0 + $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="atkrouter.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega256a3u -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAA_DFP\1.1.68\gcc\dev\atxmega256a3u" + @echo Finished building target: $@ + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "atkrouter.elf" "atkrouter.hex" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "atkrouter.elf" "atkrouter.eep" || exit 0 + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "atkrouter.elf" > "atkrouter.lss" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "atkrouter.elf" "atkrouter.srec" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "atkrouter.elf" + + + + + + + +# Other Targets +clean: + -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) + -$(RM) $(C_DEPS_AS_ARGS) + rm -rf "atkrouter.elf" "atkrouter.a" "atkrouter.hex" "atkrouter.lss" "atkrouter.eep" "atkrouter.map" "atkrouter.srec" "atkrouter.usersignatures" + \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/Debug/atkrouter.eep b/embedded/atkrouter/atkrouter/Debug/atkrouter.eep new file mode 100644 index 0000000000000000000000000000000000000000..7c166a13c19d7811fbf00e7e334ad40eebfcbe2f --- /dev/null +++ b/embedded/atkrouter/atkrouter/Debug/atkrouter.eep @@ -0,0 +1 @@ +:00000001FF diff --git a/embedded/atkrouter/atkrouter/Debug/makedep.mk b/embedded/atkrouter/atkrouter/Debug/makedep.mk new file mode 100644 index 0000000000000000000000000000000000000000..70f08c8d231f0b9953b6bca97b197db3a93bb8ed --- /dev/null +++ b/embedded/atkrouter/atkrouter/Debug/makedep.mk @@ -0,0 +1,18 @@ +################################################################################ +# Automatically-generated file. Do not edit or delete the file +################################################################################ + +atkhandler.c + +atkport.c + +fastmath.c + +main.c + +pin.c + +ringbuffer.c + +uartport.c + diff --git a/embedded/atkrouter/atkrouter/atkhandler.c b/embedded/atkrouter/atkrouter/atkhandler.c new file mode 100644 index 0000000000000000000000000000000000000000..e97d17ce068cbdd16b0e95aeb8d19a1cc414ae06 --- /dev/null +++ b/embedded/atkrouter/atkrouter/atkhandler.c @@ -0,0 +1,136 @@ +/* +* atkhandler.c +* +* Created: 3/12/2018 11:55:30 AM +* Author: Jake +*/ + +#include "hardware.h" +#include "atkhandler.h" + +int32_t steps; + +void atk_handle_packet(uint8_t *packet, uint8_t length){ + // dirty debug reply + //atk_return_packet(packet, length); + // through packet + int i = 0; + int atk_handler_state = ATK_HANDLER_OUTSIDE; + uint8_t testReply[4] = {127, 12, 24, 48}; + + while(i < length){ // prep for the messy double switch :| + switch (atk_handler_state){ + case ATK_HANDLER_OUTSIDE: + if (packet[i] == ATK_END_ROUTE_DELIMITER){ + atk_handler_state = ATK_HANDLER_INSIDE; + } + i ++; + break; + + case ATK_HANDLER_INSIDE: + switch (packet[i]){ + case DELIM_KEY_TEST: + // see the packet, make sure you're not doing something else with this light + atk_reply_packet(packet, testReply, 4); + i ++; + break; + + case DELIM_KEY_RESET: + CCP = CCP_IOREG_gc; + RST.CTRL = RST_SWRST_bm; + break; + + case DELIM_KEY_TRAPEZOID: + //pin_toggle(&stlerr); + break; + + default: + // probably an error + i ++; + break; + } // end interior switch + break; + + default : + // throw err + break; + } // end y/n switch + } +} + +// HERE return with address header, or from old packet with new data + +uint8_t ackPack[256]; + +void atk_reply_packet(uint8_t *opPacket, uint8_t *replyData, uint8_t replyLength){ + // find address chunk in opPacket + int i = 2; + int stop = 0; + while(i < opPacket[0]){ + if(opPacket[i] == ATK_END_ROUTE_DELIMITER){ + stop = i; + break; + } + i ++; + } + + uint8_t ackLength = stop + replyLength + 1; + ackPack[0] = ackLength; + + if(stop){ + // reverse the address header + for(int a = stop - 1, b = 1; a >= 1; a--, b++){ + ackPack[b] = opPacket[a]; + } + // and append the end block + ackPack[stop] = ATK_END_ROUTE_DELIMITER; + // now fill with provided reply data + for(int u = 0; u <= replyLength; u ++){ + ackPack[u + stop + 1] = replyData[u]; + } + // checking the port exists, send it out + if(ackPack[1] >= SYSTEM_NUM_UPS){ + ackPack[1] = SYSTEM_NUM_UPS - 1; + } + uart_sendchars_buffered(ups[ackPack[1]], ackPack, ackPack[0]);//ups[ackPack[1]], ackPack, ackLength); + } +} + +void atk_return_packet(uint8_t *packet, uint8_t length){ + //uart_sendchar_buffered(ups[1], 120); + //uart_sendchars_buffered(ups[1], packet, length); + // using this placeholder + ackPack[0] = length; + // find route header + int i = 2; + int stop = 0; + while(i < length){ + if(packet[i] == ATK_END_ROUTE_DELIMITER){ + stop = i; + break; + } + i ++; + } + // do the business + if(stop){ + // reverse the address header + for(int a = stop - 1, b = 1; a >= 1; a--, b++){ + ackPack[b] = packet[a]; + } + // fill the rest with same packet data + ackPack[stop] = ATK_END_ROUTE_DELIMITER; + for(int u = stop; u < length; u ++){ + ackPack[u] = packet[u]; + } + // checking the packet exists, send it out + if(ackPack[1] >= SYSTEM_NUM_UPS){ + ackPack[1] = SYSTEM_NUM_UPS - 1; + } + uart_sendchars_buffered(ups[ackPack[1]], ackPack, ackPack[0]); + // NOW: + // looking for justice: why no return packet on double length hop? + // debug with 2nd ftdi + //uart_sendchar_buffered(ups[1], 121); + //uart_sendchars_buffered(ups[1], ackpack, length); + } +} \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/atkhandler.h b/embedded/atkrouter/atkrouter/atkhandler.h new file mode 100644 index 0000000000000000000000000000000000000000..d676f9a5740f698671fd9ce71379ad2f7f834d68 --- /dev/null +++ b/embedded/atkrouter/atkrouter/atkhandler.h @@ -0,0 +1,27 @@ +/* + * atkhandler.h + * + * Created: 3/12/2018 11:55:40 AM + * Author: Jake + */ + + +#ifndef ATKHANDLER_H_ +#define ATKHANDLER_H_ + +#include <avr/io.h> + +#define ATK_HANDLER_OUTSIDE 0 +#define ATK_HANDLER_INSIDE 1 + +#define DELIM_KEY_TEST 127 // toggles a light, to test network +#define DELIM_KEY_RESET 128 + +#define DELIM_KEY_TRAPEZOID 131 + +void atk_handle_packet(uint8_t *packet, uint8_t length); + +void atk_reply_packet(uint8_t *opPacket, uint8_t *replyData, uint8_t replyLength); +void atk_return_packet(uint8_t *packet, uint8_t length); + +#endif /* atkHANDLER_H_ */ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/atkport.c b/embedded/atkrouter/atkrouter/atkport.c new file mode 100644 index 0000000000000000000000000000000000000000..8dff64b27b63d156f2ef67f07c2a63461ee8e119 --- /dev/null +++ b/embedded/atkrouter/atkrouter/atkport.c @@ -0,0 +1,123 @@ +/* + * atkport.c + * + * Created: 2/23/2018 9:17:48 AM + * Author: Jake + */ + +#include "atkport.h" +#include "hardware.h" +#include "fastmath.h" + +void atkport_init(atkport_t *atkp, uint8_t portnum, uartport_t *uart){ + atkp->uart = uart; + atkp->portnum = portnum; + + atkport_reset(atkp); +} + +void atkport_reset(atkport_t *atkp){ + atkp->packet_num = 0; + atkp->packets_ready = 0; + atkp->packet_state = ATKPORT_OUTSIDE_PACKET; + atkp->packet_position = 0; + + pin_set(atkp->uart->stlrx); + pin_set(atkp->uart->stltx); +} + +void atkport_scan(atkport_t *atkp, uint8_t maxpackets){ + // scan through for completely received packets + while(atkp->packets_ready <= maxpackets){ + // check that we have bytes to read out of the buffer + if(atkp->uart->rbrx->head == atkp->uart->rbrx->tail){ // direct access, rather than through rbempty() shaves 2us + pin_set(atkp->uart->stlrx); + break; + } else { + // pull bytes out of buffer into the packet structure + atkp->packets[atkp->packet_num][atkp->packet_position] = rb_get(atkp->uart->rbrx); + atkp->packet_position ++; + // now segment, point to them + if(atkp->packet_position >= atkp->packets[atkp->packet_num][0]){ + // length is 1st byte, like array[n] not array[n-1] + // now volley for next pass + // packet_num is index of head of packet buffer (just an array) + atkp->packet_num = fastModulo((atkp->packet_num + 1), ATKPORT_NUM_STATIC_PACKETS); // inc. and loop + // packets_ready is the number of ready-state packets in that buffer (array) + atkp->packets_ready ++; + // the position, in bytes, where we are currently operating. + // at this point, we have come to the end, so we're resetting counter for the next + atkp->packet_position = 0; + } + } + } + // end 1st scan for packets, now we know we have atkport->packet_num packets completely received + // now we handle those packets + while(atkp->packets_ready > 0){ + // the particular packet index + uint32_t p = fastModulo((atkp->packet_num + ATKPORT_NUM_STATIC_PACKETS - atkp->packets_ready), ATKPORT_NUM_STATIC_PACKETS); //(atkp->packet_num + ATKPORT_NUM_STATIC_PACKETS - atkp->packets_ready) % ATKPORT_NUM_STATIC_PACKETS; + // first we shift the old pointer out (p[1] is, at the moment, the port the last node tx'd on) + atkpacket_shift_pointer(atkp->packets[p], atkp->portnum); + // now p[1] is next port + // now to handle + // [p][0] is length of packet + if(atkp->packets[p][1] == ATK_ROUTE_POINTER){ + atk_handle_packet(atkp->packets[p], atkp->packets[p][0]); + } else if(atkp->packets[p][1] == ATK_ROUTE_FLOOD){ + // loop through bytes to find pointer and increment + // now ship it out on all ports + for(int i = 0; i < ATKPORT_NUM_PORTS; i ++){ + if(i == atkp->portnum){ + // don't flood back + } else { + uart_sendchars_buffered(ups[i], atkp->packets[p], atkp->packets[p][0]); + } + } + } else { + // packet is for a particular port, + if(atkp->packets[p][1] > ATKPORT_NUM_PORTS){ + // port does not exist, throw error + // pin_clear(&stlerr); + } else { + // debug option + //uart_sendchars_buffered(&upU, atkp->packets[p], atkp->packets[p][0]); + uart_sendchars_buffered(ups[atkp->packets[p][1]], atkp->packets[p], atkp->packets[p][0]); + } + } + // debug reply (at the moment, reply is handled in atk_handle_packet + // uart_sendchars_buffered(atkp->uart, atkp->packets[p], atkp->packets[p][0]); + atkp->packets_ready --; + } +} + +void atkpacket_shift_pointer(uint8_t *packet, uint8_t portnum){ + int i = 2; + while(i < packet[0]){ // while less than length + if(packet[i] == ATK_END_ROUTE_DELIMITER){ + // put our port in tail + packet[i-1] = portnum; + break; + } else { + // shift 'em down + packet[i-1] = packet[i]; + } + i ++; + } +} + +void atkport_send_packet(uint8_t *address, uint8_t address_length, uint8_t *payload, uint8_t payloadlength){ + // 1st byte is port out + // not yet implemented, using atk_return_packet ... all of these could be cleaner +} + +// UNIT TESTS: +/* + flood packets + multiple receptions? handle in app? + packets no end addr bar delimiter, packets no pointer, general white noise + packets varying length + packets wrong length ? very hard to catch w/o hella state ... timeout? + packets no end addr delimiter? + packets to ports not existing + // next: write javascript terminal packet builder for unit tests! +*/ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/atkport.h b/embedded/atkrouter/atkrouter/atkport.h new file mode 100644 index 0000000000000000000000000000000000000000..3a6143b68267b86c85dec720dff0761cf589cfe2 --- /dev/null +++ b/embedded/atkrouter/atkrouter/atkport.h @@ -0,0 +1,47 @@ +/* + * atkport.h + * + * Created: 2/23/2018 9:17:34 AM + * Author: Jake + */ + + +#ifndef ATKPORT_H_ +#define ATKPORT_H_ + +#include "uartport.h" +#include "pin.h" + +#define ATKPORT_NUM_STATIC_PACKETS 8 +#define ATKPORT_NUM_PORTS 6 + +#define ATKPORT_OUTSIDE_PACKET 0 +#define ATKPORT_INSIDE_PACKET 1 + +#define ATK_END_ROUTE_DELIMITER 255 +#define ATK_ROUTE_POINTER 254 +#define ATK_ROUTE_FLOOD 253 + +typedef struct{ + uartport_t *uart; + + uint8_t portnum; // which port are we + + uint32_t packet_num; + uint32_t packet_position; + uint32_t packets_ready; + uint32_t packet_state; + uint8_t packets[ATKPORT_NUM_STATIC_PACKETS][256]; // packets for handling by app +}atkport_t; + +void atkport_init(atkport_t *atkp, uint8_t portnum, uartport_t *uart); + +void atkport_reset(atkport_t *atkp); + +void atkport_scan(atkport_t *atkp, uint8_t maxpackets); + +void atkpacket_shift_pointer(uint8_t *packet, uint8_t portnum); + +void atkport_send_packet(uint8_t *address, uint8_t address_length, uint8_t *payload, uint8_t payloadlength); + +#endif /* atkPORT_H_ */ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/atkrouter.componentinfo.xml b/embedded/atkrouter/atkrouter/atkrouter.componentinfo.xml new file mode 100644 index 0000000000000000000000000000000000000000..f88fc3663794ad457842b02ffa8e9e87a5cbaf79 --- /dev/null +++ b/embedded/atkrouter/atkrouter/atkrouter.componentinfo.xml @@ -0,0 +1,86 @@ +<?xml version="1.0" encoding="utf-8"?> +<Store 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<SubType>compile</SubType> + </Compile> + <Compile Include="ringbuffer.c"> + <SubType>compile</SubType> + </Compile> + <Compile Include="ringbuffer.h"> + <SubType>compile</SubType> + </Compile> + <Compile Include="uartport.c"> + <SubType>compile</SubType> + </Compile> + <Compile Include="uartport.h"> + <SubType>compile</SubType> + </Compile> + </ItemGroup> + <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" /> +</Project> \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/fastmath.c b/embedded/atkrouter/atkrouter/fastmath.c new file mode 100644 index 0000000000000000000000000000000000000000..91d749c7d4d98df07849944e54772b75852596fc --- /dev/null +++ b/embedded/atkrouter/atkrouter/fastmath.c @@ -0,0 +1,11 @@ +/* + * fastmath.c + * + * Created: 6/20/2018 12:38:38 PM + * Author: Jake + */ + +int fastModulo(int dividend, int divisor){ + // divisor must be a power of 2! + return dividend & (divisor - 1); +} \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/fastmath.h b/embedded/atkrouter/atkrouter/fastmath.h new file mode 100644 index 0000000000000000000000000000000000000000..d1c2cb1b34048c184621f5446f18901c8a8a1272 --- /dev/null +++ b/embedded/atkrouter/atkrouter/fastmath.h @@ -0,0 +1,14 @@ +/* + * fastmath.h + * + * Created: 6/20/2018 12:35:50 PM + * Author: Jake + */ + + +#ifndef FASTMATH_H_ +#define FASTMATH_H_ + +int fastModulo(int dividend, int divisor); + +#endif /* FASTMATH_H_ */ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/hardware.h b/embedded/atkrouter/atkrouter/hardware.h new file mode 100644 index 0000000000000000000000000000000000000000..c64c358b331ce1a144c8d580897e6fb714720d16 --- /dev/null +++ b/embedded/atkrouter/atkrouter/hardware.h @@ -0,0 +1,104 @@ +/* + * hardware.h + * + * Created: 6/18/2018 12:18:05 PM + * Author: Jake + */ + + +#ifndef HARDWARE_H_ +#define HARDWARE_H_ + +#include "pin.h" +#include "ringbuffer.h" +#include "uartport.h" +#include "atkport.h" +#include "atkhandler.h" + +// results in 0.75MBaud +#define SYSTEM_BAUDA 3 +#define SYSTEM_BAUDB 0 +#define SYSTEM_NUM_UPS 6 + +#define PACKUSB_NUM_STATICPACKETS 6 + +pin_t stlclk; +pin_t stlerr; + +// UP USB (UP5) + +ringbuffer_t upUrbrx; +ringbuffer_t upUrbtx; + +uartport_t upU; + +pin_t upUrxled; // don't exist +pin_t upUtxled; + +atkport_t atkp5; + +// UP0 + +ringbuffer_t up0rbrx; +ringbuffer_t up0rbtx; + +uartport_t up0; + +pin_t up0rxled; +pin_t up0txled; + +atkport_t atkp0; + +// UP1 + +ringbuffer_t up1rbrx; +ringbuffer_t up1rbtx; + +uartport_t up1; + +pin_t up1rxled; +pin_t up1txled; + +atkport_t atkp1; + +// UP2 + +ringbuffer_t up2rbrx; +ringbuffer_t up2rbtx; + +uartport_t up2; + +pin_t up2rxled; +pin_t up2txled; + +atkport_t atkp2; + +// UP3 + +ringbuffer_t up3rbrx; +ringbuffer_t up3rbtx; + +uartport_t up3; + +pin_t up3rxled; +pin_t up3txled; + +atkport_t atkp3; + +// UP4 + +ringbuffer_t up4rbrx; +ringbuffer_t up4rbtx; + +uartport_t up4; + +pin_t up4rxled; +pin_t up4txled; + +atkport_t atkp4; + +// UPS + +uartport_t *ups[SYSTEM_NUM_UPS]; + +#endif /* HARDWARE_H_ */ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/main.c b/embedded/atkrouter/atkrouter/main.c new file mode 100644 index 0000000000000000000000000000000000000000..3a3190e239cf2b45a192004715cc815b52c85452 --- /dev/null +++ b/embedded/atkrouter/atkrouter/main.c @@ -0,0 +1,177 @@ +/* +* atkrouter.c +* +* Created: 6/17/2018 2:48:08 PM +* Author : Jake +*/ + +#include <avr/io.h> +#include <avr/interrupt.h> +#include "hardware.h" +#include "fastmath.h" + +// stlclk PA0 +// stlerr PA1 + +// do clock hotfix +// do uartports +// do cp2102n + +void clock_init(void){ + OSC.XOSCCTRL = OSC_XOSCSEL_XTAL_256CLK_gc | OSC_FRQRANGE_12TO16_gc; // select external source + OSC.CTRL = OSC_XOSCEN_bm; // enable external source + while(!(OSC.STATUS & OSC_XOSCRDY_bm)); // wait for external + OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | OSC_PLLFAC0_bm | OSC_PLLFAC1_bm; // select external osc for pll, do pll = source * 3 + OSC.CTRL |= OSC_PLLEN_bm; // enable PLL + while (!(OSC.STATUS & OSC_PLLRDY_bm)); // wait for PLL to be ready + CCP = CCP_IOREG_gc; // enable protected register change + CLK.CTRL = CLK_SCLKSEL_PLL_gc; // switch to PLL for main clock +} + +void uarts_init(void){ + // UP USB (UP5) + rb_init(&upUrbrx); + rb_init(&upUrbtx); + pin_init(&upUrxled, &PORTB, PIN4_bm, 4, 1); + pin_init(&upUtxled, &PORTB, PIN5_bm, 5, 1); + uart_init(&upU, &USARTC0, &PORTC, PIN2_bm, PIN3_bm, &upUrbrx, &upUrbtx, &upUrxled, &upUtxled); + uart_start(&upU, SYSTEM_BAUDA, SYSTEM_BAUDB); + + // UP0 + rb_init(&up0rbrx); + rb_init(&up0rbtx); + pin_init(&up0rxled, &PORTE, PIN4_bm, 4, 1); + pin_init(&up0txled, &PORTE, PIN5_bm, 5, 1); + uart_init(&up0, &USARTE1, &PORTE, PIN6_bm, PIN7_bm, &up0rbrx, &up0rbtx, &up0rxled, &up0txled); + //PORTE.PIN7CTRL = PORT_SRLEN_bm; + uart_start(&up0, SYSTEM_BAUDA, SYSTEM_BAUDB); + + // UP1 + rb_init(&up1rbrx); + rb_init(&up1rbtx); + pin_init(&up1rxled, &PORTE, PIN0_bm, 0, 1); + pin_init(&up1txled, &PORTE, PIN1_bm, 1, 1); + uart_init(&up1, &USARTE0, &PORTE, PIN2_bm, PIN3_bm, &up1rbrx, &up1rbtx, &up1rxled, &up1txled); + uart_start(&up1, SYSTEM_BAUDA, SYSTEM_BAUDB); + + // UP2 + rb_init(&up2rbrx); + rb_init(&up2rbtx); + pin_init(&up2rxled, &PORTD, PIN4_bm, 4, 1); + pin_init(&up2txled, &PORTD, PIN5_bm, 5, 1); + uart_init(&up2, &USARTD1, &PORTD, PIN6_bm, PIN7_bm, &up2rbrx, &up2rbtx, &up2rxled, &up2txled); + uart_start(&up2, SYSTEM_BAUDA, SYSTEM_BAUDB); + + // UP3 + rb_init(&up3rbrx); + rb_init(&up3rbtx); + pin_init(&up3rxled, &PORTD, PIN0_bm, 0, 1); + pin_init(&up3txled, &PORTD, PIN1_bm, 1, 1); + uart_init(&up3, &USARTD0, &PORTD, PIN2_bm, PIN3_bm, &up3rbrx, &up3rbtx, &up3rxled, &up3txled); + uart_start(&up3, SYSTEM_BAUDA, SYSTEM_BAUDB); + + // UP4 + rb_init(&up4rbrx); + rb_init(&up4rbtx); + pin_init(&up4rxled, &PORTC, PIN4_bm, 4, 1); + pin_init(&up4txled, &PORTC, PIN5_bm, 5, 1); + uart_init(&up4, &USARTC1, &PORTC, PIN6_bm, PIN7_bm, &up4rbrx, &up4rbtx, &up4rxled, &up4txled); + uart_start(&up4, SYSTEM_BAUDA, SYSTEM_BAUDB); + + ups[0] = &up0; + ups[1] = &up1; + ups[2] = &up2; + ups[3] = &up3; + ups[4] = &up4; + ups[5] = &upU; +} + +void atkps_init(void){ + atkport_init(&atkp0, 0, &up0); + atkport_init(&atkp1, 1, &up1); + atkport_init(&atkp2, 2, &up2); + atkport_init(&atkp3, 3, &up3); + atkport_init(&atkp4, 4, &up4); + atkport_init(&atkp5, 5, &upU); +} + +int main(void) +{ + clock_init(); + uarts_init(); + atkps_init(); + + // enable interrupts + sei(); + PMIC.CTRL |= PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm; + + pin_init(&stlclk, &PORTA, PIN0_bm, 0, 1); + pin_init(&stlerr, &PORTA, PIN1_bm, 1, 1); + pin_set(&stlerr); + + // runtime globals + uint32_t tck = 0; + + while (1) + { + atkport_scan(&atkp0, 2); + atkport_scan(&atkp1, 2); + atkport_scan(&atkp2, 2); + atkport_scan(&atkp3, 2); + atkport_scan(&atkp4, 2); + atkport_scan(&atkp5, 2); + + tck++; + if(!fastModulo(tck, 4096)){ + pin_toggle(&stlclk); + } + } +} + +ISR(USARTC0_RXC_vect){ + uart_rxhandler(&upU); +} + +ISR(USARTC0_DRE_vect){ + uart_txhandler(&upU); +} + +ISR(USARTE1_RXC_vect){ + uart_rxhandler(&up0); +} + +ISR(USARTE1_DRE_vect){ + uart_txhandler(&up0); +} + +ISR(USARTE0_RXC_vect){ + uart_rxhandler(&up1); +} + +ISR(USARTE0_DRE_vect){ + uart_txhandler(&up1); +} + +ISR(USARTD1_RXC_vect){ + uart_rxhandler(&up2); +} + +ISR(USARTD1_DRE_vect){ + uart_txhandler(&up2); +} + +ISR(USARTD0_RXC_vect){ + uart_rxhandler(&up3); +} + +ISR(USARTD0_DRE_vect){ + uart_txhandler(&up3); +} + +ISR(USARTC1_RXC_vect){ + uart_rxhandler(&up4); +} + +ISR(USARTC1_DRE_vect){ + uart_txhandler(&up4); +} \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/pin.c b/embedded/atkrouter/atkrouter/pin.c new file mode 100644 index 0000000000000000000000000000000000000000..071e771a5468cccc6c73bdf445068095b3dd07af --- /dev/null +++ b/embedded/atkrouter/atkrouter/pin.c @@ -0,0 +1,49 @@ +/* + * pin.c + * + * Created: 6/18/2018 12:22:50 PM + * Author: Jake + */ + +#include "pin.h" + +void pin_init(pin_t *pin, PORT_t *port, uint8_t pin_bm, uint8_t pin_pos, uint8_t inout){ + pin->port = port; + pin->pin_bm = pin_bm; + pin->pin_pos = pin_pos; + if(inout){ + pin_output(pin); + } else { + pin_input(pin); + } +} + +void pin_output(pin_t *pin){ + pin->port->DIRSET = pin->pin_bm; +} + +void pin_set(pin_t *pin){ + pin->port->OUTSET = pin->pin_bm; +} +void pin_clear(pin_t *pin){ + pin->port->OUTCLR = pin->pin_bm; +} + +void pin_toggle(pin_t *pin){ + pin->port->OUTTGL = pin->pin_bm; +} + +void pin_input(pin_t *pin){ + pin->port->DIRCLR = pin->pin_bm; +} + +void pin_pullup(pin_t *pin){ + // ? how to access PIN0CTRL, etc? +} +void pin_pulldown(pin_t *pin){ + // +} + +uint8_t pin_read(pin_t *pin){ + return (pin->port->IN & pin->pin_bm); +} \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/pin.h b/embedded/atkrouter/atkrouter/pin.h new file mode 100644 index 0000000000000000000000000000000000000000..d7ddab6e023abc0744743c66bfc7686fad2b3bac --- /dev/null +++ b/embedded/atkrouter/atkrouter/pin.h @@ -0,0 +1,34 @@ +/* + * pin.h + * + * Created: 6/18/2018 12:22:58 PM + * Author: Jake + */ + + +#ifndef PIN_H_ +#define PIN_H_ + +#include "avr/io.h" + +typedef struct { + PORT_t *port; + uint8_t pin_bm; + uint8_t pin_pos; +}pin_t; + +void pin_init(pin_t *pin, PORT_t *port, uint8_t pin_bm, uint8_t pin_pos, uint8_t inout); + +void pin_output(pin_t *pin); +void pin_set(pin_t *pin); +void pin_clear(pin_t *pin); +void pin_toggle(pin_t *pin); + +void pin_input(pin_t *pin); +void pin_pullup(pin_t *pin); +void pin_pulldown(pin_t *pin); + +uint8_t pin_read(pin_t *pin); + + +#endif /* PIN_H_ */ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/ringbuffer.c b/embedded/atkrouter/atkrouter/ringbuffer.c new file mode 100644 index 0000000000000000000000000000000000000000..a77dc50785ca9153ce3d05a656dd190bb0a59d05 --- /dev/null +++ b/embedded/atkrouter/atkrouter/ringbuffer.c @@ -0,0 +1,72 @@ +/* + * ringbuffer.c + * + * Created: 2/7/2018 11:39:44 AM + * Author: Jake + */ + +#include "ringbuffer.h" +#include "fastmath.h" + +uint8_t rb_init(ringbuffer_t *rb){ + rb->size = RINGBUFFER_SIZE; // stuck with this, due to not having malloc, wall of skill + //rb->buffer = malloc(size); + rb_reset(rb); + return 1; +} + +uint8_t rb_reset(ringbuffer_t *rb){ + if(rb){ + rb->head = 0; + rb->tail = 0; + return 1; + } else { + return 0; + } +} + +uint8_t rb_empty(ringbuffer_t *rb){ + return (rb->head == rb->tail); +} + +uint8_t rb_full(ringbuffer_t *rb){ + // read from tail, update at head + // if head is 'just behind' tail (in ring) we have no extra space: the + return fastModulo((rb->head + 1), RINGBUFFER_SIZE) == rb->tail; +} + +uint8_t rb_freespace(ringbuffer_t *rb){ + if(rb->head >= rb->tail){ + return rb->size - (rb->head - rb->tail); + } else { + return rb->tail - rb->head - 1; + } +} + +uint8_t rb_putchar(ringbuffer_t *rb, uint8_t data){ + rb->buffer[rb->head] = data; + rb->head = fastModulo((rb->head + 1), RINGBUFFER_SIZE); // increment and loop about + return 1; +} + +uint8_t rb_putdata(ringbuffer_t *rb, uint8_t *data, uint8_t size){ + /* + if(rb_freespace(rb) >= size){ + // rb_freespace, not working? + return 0; + } else { + */ + for(int i = 0; i < size; i ++){ + rb_putchar(rb, data[i]); + } + + return 1; + //} +} + +uint8_t rb_get(ringbuffer_t *rb){ + uint8_t data = rb->buffer[rb->tail]; + rb->tail = fastModulo((rb->tail + 1), RINGBUFFER_SIZE); + return data; +} + diff --git a/embedded/atkrouter/atkrouter/ringbuffer.h b/embedded/atkrouter/atkrouter/ringbuffer.h new file mode 100644 index 0000000000000000000000000000000000000000..921c8ba7717b5eedc76175a83f87db0308e6ca5e --- /dev/null +++ b/embedded/atkrouter/atkrouter/ringbuffer.h @@ -0,0 +1,43 @@ +/* + * ringbuffer.h + * + * Created: 2/7/2018 11:39:54 AM + * Author: Jake + */ + +#ifndef RINGBUFFER_H_ +#define RINGBUFFER_H_ + +/* +a ringbuffer, +s/o https://github.com/dhess/c-ringbuf +s/o https://embeddedartistry.com/blog/2017/4/6/circular-buffers-in-cc +s/o https://www.downtowndougbrown.com/2013/01/microcontrollers-interrupt-safe-ring-buffers/ +*/ + +#include "avr/io.h" +#include <stdlib.h> // for size_t + +#define RINGBUFFER_SIZE 256 + +typedef struct{ + uint8_t buffer[256]; // static! big enough + size_t head; + size_t tail; + size_t size; +} ringbuffer_t; + +uint8_t rb_init(ringbuffer_t *rb); + +uint8_t rb_reset(ringbuffer_t *rb); + +uint8_t rb_empty(ringbuffer_t *rb); +uint8_t rb_full(ringbuffer_t *rb); +uint8_t rb_freespace(ringbuffer_t *rb); + +uint8_t rb_putchar(ringbuffer_t *rb, uint8_t data); +uint8_t rb_putdata(ringbuffer_t *rb, uint8_t *data, uint8_t size); + +uint8_t rb_get(ringbuffer_t *rb); + +#endif /* RINGBUFFER_H_ */ \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/uartport.c b/embedded/atkrouter/atkrouter/uartport.c new file mode 100644 index 0000000000000000000000000000000000000000..e1bb943a09a7a8c0062710586d16811eb2905c04 --- /dev/null +++ b/embedded/atkrouter/atkrouter/uartport.c @@ -0,0 +1,70 @@ +/* + * uartport.c + * + * Created: 6/18/2018 12:12:32 PM + * Author: Jake + */ + +#include "uartport.h" +#include "hardware.h" + +void uart_init(uartport_t *up, USART_t *uart, PORT_t *port, uint8_t pinRX_bm, uint8_t pinTX_bm, ringbuffer_t *rbrx, ringbuffer_t *rbtx, pin_t *stlrx, pin_t *stltx){ + up->uart = uart; + up->port = port; + up->pinRX_bm = pinRX_bm; + up->pinTX_bm = pinTX_bm; + up->rbrx = rbrx; + up->rbtx = rbtx; + up->stlrx = stlrx; + up->stltx = stltx; +} + +void uart_start(uartport_t *up, uint8_t BAUDA, uint8_t BAUDB){ + up->uart->BAUDCTRLA = BAUDA; + up->uart->BAUDCTRLB = BAUDB; + + up->uart->CTRLA |= USART_RXCINTLVL_MED_gc | USART_TXCINTLVL_OFF_gc | USART_DREINTLVL_OFF_gc; + + up->uart->CTRLB = USART_TXEN_bm | USART_RXEN_bm; + + // should try that parity + up->uart->CTRLC = USART_CMODE_ASYNCHRONOUS_gc | USART_PMODE_DISABLED_gc | USART_CHSIZE_8BIT_gc; + + up->port->DIRCLR = up->pinRX_bm; + up->port->DIRSET = up->pinTX_bm; + + pin_set(up->stlrx); + pin_set(up->stltx); +} + +void uart_sendchar_polled(uartport_t *up, uint8_t data){ + while(!(up->uart->STATUS & USART_DREIF_bm)); + up->uart->DATA = data; +} + +void uart_sendchar_buffered(uartport_t *up, uint8_t data){ + rb_putchar(up->rbtx, data); + pin_clear(up->stltx); + up->uart->CTRLA |= USART_DREINTLVL_MED_gc; +} + +void uart_sendchars_buffered(uartport_t *up, uint8_t *data, uint8_t length){ + rb_putdata(up->rbtx, data, length); + pin_clear(up->stltx); + up->uart->CTRLA |= USART_DREINTLVL_MED_gc; +} + +void uart_rxhandler(uartport_t *up){ + pin_clear(up->stlrx); + uint8_t data = up->uart->DATA; + rb_putchar(up->rbrx, data); +} + +void uart_txhandler(uartport_t *up){ + if(!rb_empty(up->rbtx)){ + up->uart->DATA = rb_get(up->rbtx); + } else { + up->uart->CTRLA = USART_DREINTLVL_OFF_gc | USART_RXCINTLVL_MED_gc; + pin_set(up->stltx); + } +} \ No newline at end of file diff --git a/embedded/atkrouter/atkrouter/uartport.h b/embedded/atkrouter/atkrouter/uartport.h new file mode 100644 index 0000000000000000000000000000000000000000..72fa539b121a11546dddae9a76892d4ad2ef0315 --- /dev/null +++ b/embedded/atkrouter/atkrouter/uartport.h @@ -0,0 +1,42 @@ +/* + * uartport.h + * + * Created: 6/18/2018 12:12:43 PM + * Author: Jake + */ + + +#ifndef UARTPORT_H_ +#define UARTPORT_H_ + +#include "avr/io.h" +#include "ringbuffer.h" +#include "pin.h" + +typedef struct{ + USART_t *uart; + PORT_t *port; + + uint8_t pinRX_bm; + uint8_t pinTX_bm; + + ringbuffer_t *rbrx; + ringbuffer_t *rbtx; + + pin_t *stlrx; + pin_t *stltx; + +}uartport_t; + +void uart_init(uartport_t *up, USART_t *uart, PORT_t *port, uint8_t pinRX_bm, uint8_t pinTX_bm, ringbuffer_t *rbrx, ringbuffer_t *rbtx, pin_t *stlrx, pin_t *stltx); + +void uart_start(uartport_t *up, uint8_t BAUDA, uint8_t BAUDB); + +void uart_sendchar_polled(uartport_t *up, uint8_t data); +void uart_sendchar_buffered(uartport_t *up, uint8_t data); +void uart_sendchars_buffered(uartport_t *up, uint8_t *data, uint8_t length); + +void uart_rxhandler(uartport_t *up); +void uart_txhandler(uartport_t *up); + +#endif /* UARTPORT_H_ */ \ No newline at end of file diff --git a/embedded/mkrouter-v06/.vs/mkrouter-v06/v14/.atsuo b/embedded/mkrouter-v06/.vs/mkrouter-v06/v14/.atsuo index 015a3c61f290f890c224a3d309aacaf268d807a2..b667abd73c7c27fb8c5b6e29bdf3c7730ebcd1cb 100644 Binary files a/embedded/mkrouter-v06/.vs/mkrouter-v06/v14/.atsuo and b/embedded/mkrouter-v06/.vs/mkrouter-v06/v14/.atsuo differ diff --git a/embedded/mkrouter-v06/mkrouter-v06/hardware.h b/embedded/mkrouter-v06/mkrouter-v06/hardware.h index 8c0fc233ff72fb02cea3899e141ff21cd5fd25c4..99068c25a12421db6d1c705e6f8d1e9e5bffb1d1 100644 --- a/embedded/mkrouter-v06/mkrouter-v06/hardware.h +++ b/embedded/mkrouter-v06/mkrouter-v06/hardware.h @@ -30,10 +30,12 @@ #define HARDWARE_ON_PERIPHERAL_C 0x2 #define HARDWARE_ON_PERIPHERAL_D 0x3 -// use BAUD_SYSTEM 63018 for FTDI-Limited 115200 baudrate // ~ 4.2us bit period -// use BAUD_SYSTEM 22000 for 2MBaud // -// use BAUD_SYSTEM 45000 for 961538 -#define BAUD_SYSTEM 45000 +// use BAUD_SYSTEM 63019 for FTDI-Limited 115200 baudrate // ~ 4.2us bit period +// use BAUD_SYSTEM 60502 for 230400 +// use BAUD_SYSTEM 55469 for 460800 +// use BAUD_SYSTEM 45403 for 921600 + +#define BAUD_SYSTEM 63019 /* USB PINS diff --git a/embedded/mkrouter-v06/mkrouter-v06/main.c b/embedded/mkrouter-v06/mkrouter-v06/main.c index 197ba1ec8aa0d52b33d7583c27330dadd5d4389b..15739660b5f68f73a3bd15e37d0ea4d1fd9c4dc8 100644 --- a/embedded/mkrouter-v06/mkrouter-v06/main.c +++ b/embedded/mkrouter-v06/mkrouter-v06/main.c @@ -230,8 +230,6 @@ int main(void) if(pCdc->IsConfigured(pCdc) != 0){ main_b_cdc_enable = true; } - - uart_sendchar_buffered(&up0, 85); // if config is config, and port is opened if(main_b_cdc_enable){ diff --git a/embedded/mkrouter-v06/mkrouter-v06/sam_ba_monitor.c b/embedded/mkrouter-v06/mkrouter-v06/sam_ba_monitor.c index 8e399a938f348fae2cb06c5e15997ad21e2091e0..75d4b770edb21f387451a7863061361ff4025bbb 100644 --- a/embedded/mkrouter-v06/mkrouter-v06/sam_ba_monitor.c +++ b/embedded/mkrouter-v06/mkrouter-v06/sam_ba_monitor.c @@ -290,8 +290,8 @@ static void sam_ba_monitor_loop(void) if(length > 0 && !usbComOpen){ usbComOpen = 1; pin_clear(&stlUsb); - uint8_t hello[2] = {0,0}; - sam_ba_putdata(ptr_monitor_if, &hello, 2); + // uint8_t hello[2] = {0,0}; + // sam_ba_putdata(ptr_monitor_if, &hello, 2); return; }