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The Physical Computing Design tool is an integrated design tool for the design, simulation, optimization and fabrication of reconfigurable computing systems.
Traditional electronics design workflows follow a three stage sequential linear process that starts with the design of the system, then the analysis and simulation, and finally the fabrication and testing of these systems. Very often these stages are executed independently from each other, using different tools and sometimes different teams, making it very hard to translate the feedback from the simulation or testing stages into viable design amendments. This results in the design workflow, which is an inherently iterative process, being be a very tedious and inefficient process.
Therefore, we present an integrated, closed loop physical computing design tool where one can design, simulate, optimize and fabricate reconfigurable computing systems.
The following steps explain in detail the proposed design workflow:
1. **Design**: The first step is to place the DICE nodes and visualize the 3D assembly of the computing system.
2. **Programming**: Next, one should select each node and specify the node details (code/program, processor, connected neighbors, starting state.. etc).
3. **Analysis**: While placing multiple parts (an assembly), an analysis of the whole computation graph is automatically generated in realtime (average computation per frame, communication bottlenecks, connectivity graph, hierarchal graph), and custom code for application specific analysis could be added. Based this analysis, design recommendation are generated and displayed. For example, using another type of processor, adding extra nodes to divide the computation of overloaded nodes into two, finding more efficient routing for data transfer.
4. **Optimization**: If one wants to further optimize the reconfigurable computing system, the performance projection graph tool visualizes how each hardware and software decision/variable is affecting the projected performance (energy use, speed, cost). There, one describes each input variable as a distribution (normal, categorical..) and a probabilistic programming model is used to infer what is the optimal hardware configuration for the given software workflow.
5. **Simulation**: The simulation window has a visualization of the state and output of the DICE computation. This is either the output of the simulation of DICE computation on the computer before assembling and building the system or later visualizing the data sent back from the DICE system.
6. **Fabrication**: In parallel to the previous steps, the assembly realtime control window makes it very easily to control the assembler and fabricate, program, test the designed systems in realtime and to get feedback and amend the system accordingly.
This novel integrated design workflow paves the way for the design of discrete integrated circuits but also reconfigurable computing systems that can change and evolve while execution as needed.
- **"Physical Computing Interface"**
- [Assembler Control Demo](https://amiraa.pages.cba.mit.edu/physical-computing-design-tools/01_Code/physical_computing_interface/index.html)
- [Voxel Simulation Demo](https://amiraa.pages.cba.mit.edu/physical-computing-design-tools/01_Code/physical_computing_interface/indexSimulation.html)
- [Convolutional Neural Network (CNN) Demo](https://amiraa.pages.cba.mit.edu/physical-computing-design-tools/01_Code/physical_computing_interface/demos/indexDNN.html)
- **"Performance Calculation Graph"** demo lives [here.](https://amiraa.pages.cba.mit.edu/physical-computing-design-tools/01_Code/physical_computing_interface/probabilisticProjections/index.html)
- [Distributed Deep Neural Networks](https://gitlab.cba.mit.edu/amiraa/ddnn)
- UR10 voxel Assembly [demo.](https://amiraa.pages.cba.mit.edu/physical-computing-design-tools/01_Code/physical_computing_interface/assembly/standAloneAssembly.html)
### Capabilities and Updates
- Design
- Parametric grid definition (cubic, hexagonal, dice)
- Assembly/timeline
- Timeline for future morphing computing
- UR10
- Graph
- Hierarchy
- Automatic neighborhood
- highlights
- Computing
- Asynchronous code propagation (distributed max example)
- Simple test case find max value distributed
- Min cut max flow concept study neighborhood
- Hardware optimization
- see section below.
- Improved UI and integration
- Radial menu
- Json propagation
- Highlight selected node
- switch windows
- Applications
- voxel design tools
- Convolutional neural networks
---
## Applications
- The most efficient applications for dice are those who need reconfiguration white running, examples:
- probabilistic programming (Gamalon)
- more computing power while assembling voxels
- Neural Networks?
### 1- Voxel Simulation

### 2- Convolutional Neural Networks

#### Probabilistic Programming
- [Gamalon](https://gamalon.com/)
- Using Dice pieces to do **inference**
- in order to find the best configuration based on its performance
- other tasks
- [WebPPL: ](http://webppl.org/) probabilistic programming for the web
- Probabilistic Graphical Models
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In order to map the hardware architecture to an input dataflow program or computation graph, I modeled the hardware and software models as probabilistic graphical model, and used probabilistic programming to infer the best hardware architecture choices that will optimize the speed, energy and cost of the system.
I used [WebPPL](http://dippl.org/chapters/02-webppl.html) a probabilistic programming language in javascript. I model the variables I want to infer as if they come from different types of distributions that integrate our priors in them. In the following example I am using markov chain monte carlo as an inference method.
[The demo lives here.](https://amiraa.pages.cba.mit.edu/physical-computing-design-tools/01_Code/physical_computing_interface/probabilisticProjections/index.html)
The structure of the probabilistic program looks like this:
```javascript
var model=function (){
var chipType=function () { return uniformDraw(["STM32F412","samd51j19","samd51j20","MAX32660","STM32F412","XMEGA"])};
var chip=processors.type[chipType()];
//display(chip.name);
var ram=chip.ram;
var cyclesPerSecond =chip.cyclesPerSecond;
var bitsPerSecond =chip.bitsPerSecond ;
var costPerChip =chip.costPerChip ;
var flopsPerWatt =chip.flopsPerWatt ;
var interconnect=mem(function (model) { return uniformDraw([2,4,6])});
var nodesNumber= mem(function (model) { return uniformDraw([10,20,30,40,50])});
var dataExchangeSize=mem(function (model) {return gaussian(1e3, 10)});
var memoryPerComputation=mem(function (model) {return gaussian(10e3, 10)});
var numberofComputations=mem(function (model) {return gaussian(200, 10)}); //nodes of similar computations
var computation = mem(function (model) {return gaussian(100, 20)});
var maxNumberOfInterconnects= mem(function (model) {return gaussian(10, 2)});
doCalculation();
var speed=computationTime+communicationTime; //frame
var cost=nodesNumber("DICE")*costPerChip;
var energy= 1 / flopsPerWatt*numberofNodesNeeded*computationTime;//per frame
condition(speed<0.0012 && cost<180);
// return [speed,cost,energy]
if(result==1){
return chip.name;
}else if(result==2){
return interconnect("DICE");
}else{
return nodesNumber("DICE");
}
}
var result=3;
var options = {method: 'MCMC', kernel: 'MH', samples: 10000}
var dist = Infer(options, model)
viz(dist)
display('Expected nodesNumber: ' + expectation(dist))
expectation(dist)
```
Until now I have a dummy computation model. Next steps would be to get a complex computational graph and for each part infer the best hardware architecture for it. Moreover, if the computation graph changes through time one can also alter the hardware architecture to respond to these changes.
## TODO and Next Steps:
- [ ] **Documentation**:
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- [ ] readme page:
- [ ] change make it multiple pages
- [ ] **General workflow/UI**:
- [ ] closure and prototypes for everything
- [ ] Switch windows
- [ ] modularize current windows
- [ ] programmatically call and add windows to UI
- [ ] add destroy function for each closure
- [ ] Global selection
- [ ] expose global variables
- [ ] when none of the nodes is selected you can edit the globals
- [ ] grids (destroy all three js and create a new one)
- [ ] voxel size
- [ ] history of add and remove?
- [ ] Hierarchy
- [ ] place multiple voxels
- [ ] change code of multiple voxels
- [ ] select multiple dice pieces
- [ ] create groups
- [ ] Scaling
- [ ] stress testing scaling
- [ ] **Assembly**:
- [ ] general
- [ ] fix errors
- [ ] UR arm
- [ ] real life connection
- [ ] code (from python? or just call python scripts??)
- [ ] meso dice
- [ ] work with zach on it
- [ ] swarm assembly
- [ ] bill-e assembly of the computation elements
- [ ] structural robotics
- [ ] Jiri assembler
- [ ] cad? visualize
- [ ] fix grid
- [ ] **Computation and optimization**:
- [ ] load c++ or other code
- [ ] automatically computation delay and communication cost
- [ ] Optimization strategy
- [ ] simple show bottlenecks in computation or communication
- [ ] alternatives and suggestions
- [ ] local suggestions to divide the computation into two nodes?
- [ ] shape discovery
- [ ] add window of probabilistic search parameters
- [ ] Restructuring code and automatically divide into distributed
- [ ] **Applications/Demonstrations**:
- [ ] AI
- [ ] Convolutional Neural networks
- [ ] highlight bottleneck and communication delay
- [ ] Probabilistic Programming
- [ ] add window optimization
- [ ] Distributed optimization/belief propagation
- [ ] Bayesian optimization
- [ ] Voxel Design
- [ ] add a walking robot
- [ ] Morphing computing systems examples
- [ ] Voxel land
- [ ] a big structure getting assembled assembled while getting bigger
- [ ] computation getting bigger
- [ ] dynamic physics simulation
- [ ] when from one part to another so does the placement of the computing systems